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| december 2004 1/131 rev. 2.0 st7lite1 8-bit mcu with single voltage flash memory, data eeprom, adc, 4 timers, spi memories ? 4 kbytes single voltage extended flash (xflash) program memory with read-out pro- tection, in-circuit programming and in-appli- cation programming (icp and iap). 10k write/ erase cycles guaranteed, data retention: 20 years at 55c. ? 256 bytes ram ? 128 bytes data e 2 prom with read-out protec- tion. 300k write/erase cycles guaranteed, data retention: 20 years at 55c. clock, reset and supply management ? enhanced reset system ? enhanced low voltage supervisor (lvd) for main supply and an auxiliary voltage detector (avd) with interrupt ca pability for implement- ing safe power-down procedures ? clock sources: internal 1% rc oscillator (on some devices), crystal/ceramic resonator or external clock ? internal 32-mhz input clock for auto-reload timer ? optional x4 or x8 pll for 4 or 8 mhz internal clock ? five power saving modes: halt, active-halt, auto wake-up from halt, wait and slow i/o ports ? up to 15 multifunctional bidirectional i/o lines ?7 high sink outputs 4 timers ? configurable watchdog timer ? two 8-bit lite timers with prescaler, 1 realtime base and 1 input capture ? one 12-bit auto-reload timer with 4 pwm outputs, input capture and output compare functions communication interface ? spi synchronous serial interface interrupt management ? 10 interrupt vectors plus trap and reset ? 15 external interrupt lines (on 4 vectors) a/d converter ? 7 input channels ? fixed gain op-amp ? 13-bit precision for 0 to 430 mv (@ 5v v dd ) ? 10-bit precision for 430 mv to 5v (@ 5v v dd ) instruction set ? 8-bit data manipulation ? 63 basic instructions with illegal opcode de- tection ? 17 main addressing modes ? 8 x 8 unsigned multiply instructions development tools ? full hardware/software development package ? dm (debug module) device summary so20 features st7lite10 st7lite15 st7lite19 program memory - bytes 4k ram (stack) - bytes 256 (128) data eeprom - bytes - - 128 peripherals lite timer with watchdog, autoreload timer, spi, 10-bit adc with op-amp lite timer with watchdog, autoreload timer with 32-mhz input clock, spi, 10-bit adc with op-amp operating supply 2.4v to 5.5v cpu frequency up to 8mhz (w/ ext osc up to 16mhz) up to 8mhz (w/ ext osc up to 16mhz and int 1mhz rc 1% pllx8/4mhz) operating temperature -40c to +85c packages so20 300? 1
table of contents 131 2/131 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 5.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 data eeprom read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 internal rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.5 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.6 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 9.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.5 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.6 auto wake up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1 table of contents 3/131 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.4 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.7 device-specific i/o port config uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2 12-bit autoreload timer 2 (at2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3 lite timer 2 (lt2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.5 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.10 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 113 13.11 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.2 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 15 device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 15.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 22 15.2 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 16 important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 16.1 execution of btjx instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 16.2 adc conversion spurious results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 16.3 a/ d converter accuracy for first conversion . . . . . . . . . . . . . . . . . . . 129 16.4 negative injection impact on adc accuracy . . . . . . . . . . . . . . . . . . . . . . . 129 st7lite1 4/131 16.5 clearing active interrupts outside interrupt routine . . . . . . . . . . . . 129 16.6 using pb4 as external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 to obtain the most recent version of this datasheet, please check at www.st.com>produ cts>technical literature>datasheet please also pay special attention to the section ?important notes? on page 128. st7lite1 5/131 1 introduction the st7lite1 is a member of the st7 microcon- troller family. all st7 devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. the st7lite1 features flash memory with byte-by-byte in-circuit programming (icp) and in- application programm ing (iap) capability. under software control, the st7lite1 device can be placed in wait, slow, or halt mode, reduc- ing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. for easy reference, all parametric data are located in section 13 on page 91 .the devices feature an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm reg- isters, refer to the st7 icc protocol reference manual. figure 1. general block diagram 8-bit core alu address and data bus osc1 osc2 reset port a internal clock control ram (256 bytes) pa7:0 (8 bits) v ss v dd power supply program (4k bytes) lvd memory pll x 8 ext. 1mhz pll int. 1mhz 8-bit lite timer 2 port b spi pb6:0 (7 bits) data eeprom (128 bytes) 1% rc osc to 16mhz adc + opamp 12-bit auto-reload timer 2 clkin / 2 or pll x4 8mhz -> 32mhz watchdog debug module 1 st7lite1 6/131 2 pin description figure 2. 20-pin so package pinout 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v ss v dd ain5/pb5 clkin/ain4/pb4 mosi/ain3/pb3 miso/ain2/pb2 sck/ain1/pb1 ss /ain0/pb0 osc1/clkin osc2 pa5 (hs)/atpwm3/iccdata pa4 (hs)/atpwm2 pa3 (hs)/atpwm1 pa2 (hs)/atpwm0 pa1 (hs)/atic pa0 (hs)/ltic (hs) 20ma high sink capability eix associated external interrupt vector 12 11 9 10 ain6/pb6 pa7(hs) pa6/mco/iccclk/break reset ei3 ei2 ei0 ei1 1 st7lite1 7/131 pin description (cont?d) legend / abbreviations for table 1 : type: i = input, o = output, s = supply in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: ? input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ? output: od = open drain, pp = push-pull the reset configuration of each pin is shown in bold which is valid as lo ng as the device is in reset state. table 1. device pin description pin no. pin name type level port / control main function (after reset) alternate function input output input output float wpu int ana od pp 1v ss s ground 2v dd s main power supply 3 reset i/o c t x x top priority non maskable interrupt (active low) 4 pb0/ain0/ss i/o c t x ei3 xxx port b0 adc analog input 0 or spi slave select (active low) caution: no negative current injection allowed on this pin. for details, refer to section 13.2.2 on page 92 5 pb1/ain1/sck i/o c t x xxx port b1 adc analog input 1 or spi seri- al clock caution: no negative current injection allowed on this pin. for details, refer to section 13.2.2 on page 92 6 pb2/ain2/miso i/o c t x xxx port b2 adc analog input 2 or spi mas- ter in/ slave out data 7 pb3/ain3/mosi i/o c t x ei2 xxx port b3 adc analog input 3 or spi mas- ter out / slave in data 8 pb4/ain4/clkin i/o c t x xxx port b4 adc analog input 4 or external clock input 9 pb5/ain5 i/o c t x xxx port b5 adc analog input 5 10 pb6/ain6 i/o c t x xxx port b6 adc analog input 6 11 pa7 i/o c t hs x ei1 x x port a7 1 st7lite1 8/131 12 pa6 /mco/ iccclk/break i/o c t x ei1 xx port a6 main clock output or in circuit communication clock or exter- nal break caution: during normal opera- tion this pin must be pulled- up, internally or exte rnally (external pull-up of 10k mandatory in noisy environment). this is to avoid entering icc mode unex- pectedly during a reset. in the application, even if the pin is configured as output, any reset will put it back in input pull-up 13 pa5 / iccdata i/o c t hs x ei1 xx port a5 in circuit communication data 14 pa4 i/o c t hs x xx port a4 15 pa3/atpwm1 i/o c t hs x ei0 xx port a3 auto-reload timer pwm1 16 pa2/atpwm0 i/o c t hs x xx port a2 auto-reload timer pwm0 17 pa1/atic i/o c t hs x xx port a1 auto-reload timer input cap- ture 18 pa0/ltic i/o c t hs x xx port a0 lite timer input capture 19 osc2 o resonator oscillator inverter output 20 osc1/clkin i resonator oscillator invert er input or external clock input pin no. pin name type level port / control main function (after reset) alternate function input output input output float wpu int ana od pp 1 st7lite1 9/131 3 register & memory map as shown in figure 3 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 256 bytes of ram, 128 bytes of data eeprom and 4 kbytes of flash pro- gram memory. the ram space includes up to 128 bytes for the stack from 180h to 1ffh. the highest address bytes contain the user reset and interrupt vectors. the flash memory contains two sectors (see fig- ure 3 ) mapped in the upper part of the st7 ad- dressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). the size of flash sector 0 and other device op- tions are configurable by option byte (refer to sec- tion 15.1 on page 121 ). important: memory locations marked as ?re- served? must never be accessed. accessing a re- seved area can have unpredictable effects on the device. figure 3. memory map 0000h ram flash memory (4k) interrupt & reset vectors hw registers 0080h 007fh 0fffh (see table 2 ) 1000h 107fh ffe0h ffffh (see table 5 ) 0180h reserved 017fh short addressing ram (zero page) 0080h 00ffh (128 bytes) data eeprom (128 bytes) f000h 1080h efffh reserved ffdfh 128 bytes stack 0100h 017fh 1 kbyte 3 kbytes sector 1 sector 0 4k flash ffffh fc00h fbffh f000h program memory 1000h 1001h rccr0 rccr1 see section 7.1 on page 23 rccr0 rccr1 see section 7.1 on page 23 ffdeh ffdfh 00ffh 01ffh 0100h reserved ram (128 bytes) reserved 0200h 0180h 01ffh 1 st7lite1 10/131 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register ffh 1) 00h 40h r/w r/w r/w 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register ffh 1) 00h 00h r/w r/w r/w 2) 0006h 0007h reserved area (2 bytes) 0008h 0009h 000ah 000bh 000ch lite timer 2 ltcsr2 ltarr ltcntr ltcsr1 lticr lite timer control/ status register 2 lite timer auto-reload register lite timer counter register lite timer control/ status register 1 lite timer input capture register 0fh 00h 00h 0x00 0000h xxh r/w r/w read only r/w read only 000dh 000eh 000fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h 0021h 0022h auto- reload timer 2 atcsr cntrh cntrl atrh atrl pwmcr pwm0csr pwm1csr pwm2csr pwm3csr dcr0h dcr0l dcr1h dcr1l dcr2h dcr2l dcr3h dcr3l aticrh aticrl trancr breakcr timer control/status register counter register high counter register low auto-reload register high auto-reload register low pwm output control register pwm 0 control/status register pwm 1 control/status register pwm 2 control/status register pwm 3 control/status register pwm 0 duty cycle register high pwm 0 duty cycle register low pwm 1 duty cycle register high pwm 1 duty cycle register low pwm 2 duty cycle register high pwm 2 duty cycle register low pwm 3 duty cycle register high pwm 3 duty cycle register low input capture register high input capture register low transfer control register break control register 0x00 0000h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 01h 00h r/w read only read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only r/w r/w 0023h to 002dh reserved area (11 bytes) 002eh wdg wdgcr watchdog control register 7fh r/w 0002fh flash fcsr flash control/status register 00h r/w 00030h eeprom eecsr data eeprom control/status register 00h r/w 0031h 0032h 0033h spi spidr spicr spicsr spi data i/o register spi control register spi control status register xxh 0xh 00h r/w r/w r/w 0034h 0035h 0036h adc adccsr adcdrh adcdrl a/d control status register a/d data register high a/d amplifier control/data low register 00h xxh 0xh r/w read only r/w 1 st7lite1 11/131 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 3. for a description of the debug module registers, see icc reference manual. 0037h itc eicr external interrupt control register 00h r/w 0038h mcc mccsr main clock contro l/status register 00h r/w 0039h 003ah clock and reset rccr sicsr rc oscillator c ontrol register system integrity control/status register ffh 0000 0xx0h r/w r/w 003bh reserved area (1 byte) 003ch itc eisr external interrupt selection register 0ch r/w 003dh to 0048h reserved area (12 bytes) 0049h 004ah awu awupr awucsr awu prescaler register awu control/status register ffh 00h r/w r/w 004bh 004ch 004dh 004eh 004fh 0050h dm 3) dmcr dmsr dmbk1h dmbk1l dmbk2h dmbk2l dm control register dm status register dm breakpoint register 1 high dm breakpoint register 1 low dm breakpoint register 2 high dm breakpoint register 2 low 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w 0051h to 007fh reserved area (47 bytes) address block register label register name reset status remarks 1 st7lite1 12/131 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on-board using in-circuit programming or in-application program- ming. the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features icp (in-circuit programming) iap (in-application programming) ict (in-circuit testing) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte read-out and write protection 4.3 programming modes the st7 can be programmed in three different ways: ? insertion in a programming tool. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) can be pro- grammed or erased. ? in-circuit programming. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) can be programmed or erased without removing the device from the application board. ? in-application programming. in this mode, sector 1 and data eeprom (if present) can be programmed or erased without removing the device from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit commu- nication) which allows an st7 plugged on a print- ed circuit board (pcb) to communicate with an ex- ternal programming device connected via cable. icp is performed in three steps: switch the st7 to icc mode (in-circuit communi- cations). this is done by driving a specific signal sequence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific reset vector which points to the st7 system memory contain- ing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface. ? download icp driver code in ram from the iccdata pin ? execute icp driver code in ram to program the flash memory depending on the icp driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in application programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). this mode is fully contro lled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc). iap mode can be used to program any memory ar- eas except sector 0, which is write/erase protect- ed to allow recovery in case errors occur during the programming operation. 1 st7lite1 13/131 flash program memory (cont?d) 4.4 icc interface icp needs a minimum of 4 and up to 6 pins to be connected to the programming tool. these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input serial data pin ? osc1: main clock input for external source (not required on devices without osc1/osc2 pins) ?v dd : application board power supply (option- al, see note 3) notes: 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another de- vice forces the signal. refer to the programming tool documentation for recommended resistor val- ues. 2. during the icp session, the programming tool must control the reset pin. this can lead to con- flicts between the programming tool and the appli- cation reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the appli- cation reset circuit in this case. when using a classical rc network with r>1k or a reset man- agement ic with open drain output and pull-up re- sistor>1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st program- ming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 pin of the st7 when the clock is not available in the ap- plication or if the selected clock option is not pro- grammed in the option byte. st7 devices with mul- ti-oscillator capability ne ed to have osc2 ground- ed in this case. 5. with the icp option disabled with st7 mdt10- epb that the external clock has to be provided on pb4. caution: during normal operation the iccclk pin must be pulled- up, internally or externally (exter- nal pull-up of 10k mandatory in noisy environ- ment). this is to avoid entering icc mode unex- pectedly during a reset. in the application, even if the pin is configured as output, any reset will put it back in input pull-up. figure 4. typical icc interface icc connector iccdata iccclk reset vdd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) st7 c l2 c l1 osc1/pb4 osc2 optional see note 1 and caution see note 2 application reset source application i/o (see note 4) (see note 5) clkin 1 st7lite1 14/131 flash program memory (cont?d) 4.5 memory protection there are two different types of memory protec- tion: read out protection and write/erase protec- tion which can be applied individually. 4.5.1 read out protection readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. both program and data e 2 memory are protected. in flash devices, this protection is removed by re- programming the option. in this case, both pro- gram and data e 2 memory are automatically erased and the device can be reprogrammed. read-out protection selection depends on the de- vice type: ? in flash devices it is enabled and removed through the fmp_r bit in the option byte. ? in rom devices it is enabled by mask option specified in the option list. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impos- sible to both overwrite and erase program memo- ry. it does not apply to e 2 data. its purpose is to provide advanced security to applications and pre- vent any change being made to the memory con- tent. warning : once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. write/erase protection is enabled through the fmp_w bit in the option byte. 4.6 related documentation for details on flash programming and icc proto- col, refer to the st7 flash programming refer- ence manual and to the st7 icc protocol refer- ence manual . 4.7 register description flash control/status register (fcsr) read/write reset value: 000 0000 (00h) 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) note: this register is reserved for programming using icp, iap or other programming methods. it controls the xflash programming and erasing op- erations. when an epb or anothe r programming tool is used (in socket or icp mode), the rass keys are sent automatically. 70 00000optlatpgm 1 st7lite1 15/131 5 data eeprom 5.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back- up for storing data. usin g the eeprom requires a basic access protocol described in this chapter. 5.2 main features up to 32 bytes programmed in the same cycle eeprom mono-voltage (charge pump) chained erase and programming cycles internal control of the global programming cycle duration wait mode management readout protection figure 5. eeprom block diagram eecsr high voltage pump 0 e2lat 0 0 0 0 0 e2pgm eeprom memory matrix (1 row = 32 x 8 bits) address decoder data multiplexer 32 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus 1 st7lite1 16/131 data eeprom (cont?d) 5.3 memory access the data eeprom memory read/write access modes are controlled by the e2lat bit of the eep- rom control/status register (eecsr). the flow- chart in figure 6 describes these different memory access modes. read operation (e2lat=0) the eeprom can be read as a normal rom loca- tion when the e2lat bit of the eecsr register is cleared. in a read cycle, the byte to be accessed is put on the data bus in less than 1 cpu clock cycle. this means that re ading data from eeprom takes the same time as reading data from eprom, but this memory cannot be used to exe- cute machine code. write operation (e2lat=1) to access the write mode, the e2lat bit has to be set by software (the e2pgm bit remains cleared). when a write access to the eeprom area occurs, the value is latched inside the 32 data latches ac- cording to its address. when pgm bit is set by the software, all the previ- ous bytes written in the data latches (up to 32) are programmed in the eeprom cells. the effective high address (row) is determined by the last eep- rom write sequence. to avoid wrong program- ming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five least significant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously. note : care should be taken during the program- ming cycle. writing to the same memory location will over-program the me mory (logical and be- tween the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the e2lat bit. it is not possible to read the latched data. this note is ilustrated by the figure 8 . figure 6. data eeprom programming flowchart read mode e2lat=0 e2pgm=0 write mode e2lat=1 e2pgm=0 read bytes in eeprom area writeupto32bytes in eeprom area (with the same 11 msb of the address) start programming cycle e2lat=1 e2pgm=1 (set by software) e2lat 01 cleared by hardware 1 st7lite1 17/131 data eeprom (cont?d) figure 7. data e 2 prom write operation note: if a programming cycle is interrupted (by software or a reset action), the integrity of the data in mem- ory is not guaranteed. byte 1 byte 2 byte 32 phase 1 programming cycle read operation impossible phase 2 read operation possible e2lat bit e2pgm bit writing data latches waiting e2pgm and e2lat to fall set by user application cleared by hardware ? row / byte ? 0 1 2 3 ... 30 31 physical address 0 00h...1fh 1 20h...3fh ... n nx20h...nx20h+1fh row definition 1 st7lite1 18/131 data eeprom (cont?d) 5.4 power saving modes wait mode the data eeprom can enter wait mode on ex- ecution of the wfi instruction of the microcontrol- ler or when the microcontroller enters active-halt mode.the data eeprom will immediately enter this mode if there is no programming in progress, otherwise the data eeprom will finish the cycle and then enter wait mode. active-halt mode refer to wait mode. halt mode the data eeprom immediately enters halt mode if the microcontroller executes the halt in- struction. ther efore the eeprom will stop the function in progress, and data may be corrupted. 5.5 access error handling if a read access occurs while e2lat=1, then the data bus will not be driven. if a write access occurs while e2lat=0, then the data on the bus will not be latched. if a programming cycle is interrupted (by software/ reset action), the memo ry data will not be guar- anteed. 5.6 data eeprom read-out protection the read-out protection is enabled through an op- tion bit (see section 15.1 on page 121 ). when this option is selected, the programs and data stored in the eeprom memory are protected against read-out (including a re-write protection). in flash devices, when this protection is removed by reprogramming the option byte, the entire pro- gram memory and eeprom is first automatically erased. note: both program memory and data eeprom are protected using the same option bit. figure 8. data eeprom programming cycle lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage 1 st7lite1 19/131 data eeprom (cont?d) 5.7 register description eeprom control/status register (eec- sr) read/write reset value: 0000 0000 (00h) bits 7:2 = reserved, forced by hardware to 0. bit 1 = e2lat latch access transfer this bit is set by software. it is cleared by hard- ware at the end of the programming cycle. it can only be cleared by software if the e2pgm bit is cleared. 0: read mode 1: write mode bit 0 = e2pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware. 0: programming finished or not yet started 1: programming cycle is in progress note : if the e2pgm bit is cleared during the pro- gramming cycle, the memory data is not guaran- teed table 3. data eeprom register map and reset values 70 000000e2late2pgm address (hex.) register label 76543210 0030h eecsr reset value 000000 e2lat 0 e2pgm 0 1 st7lite1 20/131 6 central processing unit 6.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 6.3 cpu registers the 6 cpu registers shown in figure 9 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 9. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 1 st7lite1 21/131 cpu registers (cont?d) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested usin g the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. 70 111hinzc 1 st7lite1 22/131 cpu registers (cont?d) stack pointer (sp) read/write reset value: 01ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 10 ). since the stack is 128 bytes deep, the 9 most sig- nificant bits are forced by hardware. following an mcu reset, or after a re set stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 10 . ? when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. ? on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five location s in the stack area. figure 10. stack manipulation example 15 8 00000001 70 1 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0180h stack higher address = 01ffh stack lower address = 0180h 1 st7lite1 23/131 7 supply, reset an d clock management the device includes a ran ge of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. main features clock management ? 1 mhz internal rc oscillator (enabled by op- tion byte, available on st7lite15 and st7lite19 devices only) ? 1 to 16 mhz or 32khz external crystal/ceramic resonator (selected by option byte) ? external clock input (enabled by option byte) ? pll for multiplying the frequency by 8 or 4 (enabled by option byte) ? for clock art counter only: pll32 for multi- plying the 8 mhz frequency by 4 (enabled by option byte). the 8 mhz input frequency is mandatory and can be obtained in the follow- ing ways: ?1 mhz rc + pllx8 ?16 mhz external clock (internally divided by 2) ?2 mhz. external clock (internally divided by 2) + pllx8 ?crystal oscillator with 16 mhz output fre- quency (internally divided by 2) reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd) with reset generation (enabled by option byte) ? auxiliary voltage detect or (avd) with interrupt capability for monitoring the main supply (en- abled by option byte) 7.1 internal rc oscillator adjustment the device contains an internal rc oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5v-5.5v). it must be calibrat- ed to obtain the frequency required in the applica- tion. this is done by so ftware writing a calibration value in the rccr (rc control register). whenever the microcontroller is reset, the rccr returns to its default value (ffh), i.e. each time the device is reset, the calibration value must be load- ed in the rccr. predefined calibration values are stored in eeprom for 3 and 5v v dd supply volt- ages at 25c, as shown in the following table. note: ? see ?electrical characteristics? on page 91. for more information on the frequency and accuracy of the rc oscillator. ? to improve clock stability, it is recommended to place a decoupling capacitor between the v dd and v ss pins. ? these two bytes are systematically programmed by st, including on fastrom devices. conse- quently, customers intending to use fastrom service must not use these two bytes. ? rccr0 and rccr1 calibration values will be erased if the read-out protection bit is reset after it has been set. see ?read out protection? on page 14. caution: if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. refer to application note an1324 for information on how to calibrate the rc frequency using an ex- ternal reference signal. 7.2 phase locked loop the pll can be used to multiply a 1mhz frequen- cy from the rc oscillator or the external clock by 4 or 8 to obtain f osc of 4 or 8 mhz. the pll is ena- bled and the multiplication factor of 4 or 8 is select- ed by 2 option bits. ? the x4 pll is intended for operation with v dd in the 2.4v to 3.3v range ? the x8 pll is intended for operation with v dd in the 3.3v to 5.5v range refer to section 15.1 for the option byte descrip- tion. if the pll is disabled and the rc oscillator is ena- bled, then f osc = 1mhz. if both the rc oscillator and the pll are disabled, f osc is driven by the external clock. rccr conditions st7lite19 address st7lite15 address rccr0 v dd =5v t a =25c f rc =1mhz 1000h and ffdeh ffdeh rccr1 v dd =3v t a =25c f rc =700khz 1001h and ffdfh ffdfh 1 st7lite1 24/131 phase locked loop (cont?d) figure 11. pll output frequency timing diagram when the pll is started, after reset or wakeup from halt mode or awufh mode, it outputs the clock after a delay of t startup . when the pll output signal reaches the operating frequency, the locked bit in the sicscr register is set. full pll accuracy (acc pll ) is reached after a stabilization time of t stab (see figure 11 and 13.3.4 internal rc oscillator and pll ) refer to section 7.6.4 on page 33 for a description of the locked bit in the sicsr register. 7.3 register description main clock control/status register (mccsr) read / write reset value: 0000 0000 (00h) bits 7:2 = reserved, mu st be kept cleared. bit 1 = mco main clock out enable this bit is read/write by software and cleared by hardware after a reset. this bit allows to enable the mco output clock. 0: mco clock disabled, i/o port free for general purpose i/o. 1: mco clock enabled. bit 0 = sms slow mode select this bit is read/write by software and cleared by hardware after a reset. this bit selects the input clock f osc or f osc /32. 0: normal mode (f cpu = f osc 1: slow mode (f cpu = f osc /32) rc control register (rccr) read / write reset value: 1111 1111 (ffh) bits 7:0 = cr[7:0] rc oscillator frequency ad- justment bits these bits must be written immediately after reset to adjust the rc oscillato r frequency an d to obtain an accuracy of 1%. the application can store the correct value for each voltage range in eeprom and write it to this register at start-up. 00h = maximum available frequency ffh = lowest available frequency note: to tune the oscillator, write a series of differ- ent values in the register until the correct frequen- cy is reached. the fastest method is to use a di- chotomy starting with 80h. 4/8 x freq. locked bit set t stab t lock input output freq. t startup t 70 000000 mco sms 70 cr70 cr60 cr50 cr40 cr30 cr20 cr10 cr 0 1 st7lite1 25/131 figure 12. clock management block diagram cr4 cr7 cr0 cr1 cr2 cr3 cr6 cr5 rccr f osc mccsr sms mco mco f cpu f cpu to cpu and peripherals (1ms timebase @ 8 mhz f osc ) /32 divider f osc f osc /32 f osc f ltimer 1 0 lite timer 2 counter 8-bit at timer 2 12-bit pll 8mhz -> 32mhz f cpu clkin osc2 clkin tunable oscillator 1% rc pll 1mhz -> 8mhz pll 1mhz -> 4mhz rc osc pllx4x8 /2 divider option bits osc,plloff, oscrange[2:0] osc 1-16 mhz or 32khz clkin clkin /osc1 osc /2 divider osc/2 clkin/2 clkin/2 option bits osc,plloff, oscrange[2:0] 1 st7lite1 26/131 7.4 multi-osc illator (mo) the main clock of the st7 can be generated by four different source types coming from the multi- oscillator block (1 to 16mhz or 32khz): an external source 5 crystal or ceramic resonator oscillators an internal high frequency rc oscillator each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in table 4 . refer to the electrical characteristics section for more details. external clock source in this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. note: when the multi- oscillator is not used, pb4 is selected by default as external clock. crystal/ceramic oscillators this family of oscillators has the advan tage of pro- ducing a very accurate rate on the main clock of the st7. the selection with in a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.1 on page 121 for more details on the frequency ranges). in this mode of the multi-oscil- lator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization ti me. the loading capaci- tance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. internal rc oscillator in this mode, the tunabl e 1%rc oscillator is used as main clock source. the two oscillator pins have to be tied to ground. table 4. st7 clock sources hardware configuration external clock crystal/ceramic resonators internal rc oscillator osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7 1 st7lite1 27/131 7.5 reset sequence manager (rsm) 7.5.1 introduction the reset sequence manager includes three re- set sources as shown in figure 14 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 13 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (see table below) reset vector fetch the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilise an d ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay is automatically select- ed depending on the clock source chosen by op- tion byte: the reset vector fetch phase duration is 2 clock cycles. if the pll is enabled by option byte, it outputs the clock after an additional delay of t startup (see figure 11 ). figure 13. reset sequence phases 7.5.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristic section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 15 ). this de- tection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 14. reset block diagram clock source cpu clock cycle delay internal rc oscillator 256 external clock (connected to clkin pin) 256 external crystal/ceramic oscillator (connected to osc1/osc2 pins) 4096 reset active phase internal reset 256 or 4096 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter 1 st7lite1 28/131 reset sequence manager (cont?d) the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. 7.5.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specified for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to the reset pin. 7.5.4 internal low voltage detector (lvd) reset two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd st7lite1 30/131 figure 17. reset and supply management block diagram low voltage detector (lvd) auxiliary voltage detector (avd) reset v ss v dd reset sequence manager (rsm) avd interrupt request system integrity management watchdog sicsr timer (wdg) avdie avdf status flag 0 0 lvdrf locked wdgrf 0 1 st7lite1 31/131 system integrity management (cont?d) 7.6.2 auxiliary voltage detector (avd) the voltage detector function (avd) is based on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main sup- ply voltage (v avd ). the v it-(avd) reference value for falling voltage is lower than the v it+(avd) refer- ence value for rising voltage in order to avoid par- asitic detection (hysteresis). the output of the avd comparator is directly read- able by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. caution : the avd functions only if the lvd is en- abled through the option byte. 7.6.2.1 monitoring the v dd main supply the avd voltage threshold value is relative to the selected lvd threshold configured by option byte (see section 15.1 on page 121 ). if the avd interrupt is enabled, an interrupt is gen- erated when the voltage crosses the v it+(lvd) or v it-(avd) threshold (avdf bit is set). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcon- troller. see figure 18 . figure 18. using the avd to monitor v dd v dd v it+(avd) v it-(avd) avdf bit 01 reset if avdie bit = 1 v hyst avd interrupt request interrupt cleared by v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 0 1 hardware interrupt cleared by reset 1 st7lite1 32/131 system integrity management (cont?d) 7.6.3 low power modes 7.6.3.1 interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is re- set (rim instruction). mode description wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the sicsr register is frozen. the avd remains active. interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no 1 st7lite1 33/131 system integrity management (cont?d) 7.6.4 register description system integrity (si) control/status register (sicsr) read/write reset value: 0000 0xx0 (0xh) bit 7:5 = reserved, must be kept cleared. bit 4 = wdgrf watchdog reset flag this bit indicates that the last reset was generat- ed by the watchdog peripheral. it is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. bit 3 = locked pll locked flag this bit is set and cleared by hardware. it is set au- tomatically when the pll reaches its operating fre- quency. 0: pll not locked 1: pll locked bit 2 = lvdrf lvd reset flag this bit indicates that the last reset was generat- ed by the lvd block. it is set by hardware (lvd re- set) and cleared by software (by reading). when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 1 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is gen- erated when the avdf bit is set. refer to figure 18 and to section 7.6.2.1 for additional details. 0: v dd over avd threshold 1: v dd under avd threshold bit 0 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag is set. the pending interrupt information is automati- cally cleared when software enters the avd inter- rupt routine. 0: avd interrupt disabled 1: avd interrupt enabled application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. 70 000 wdg rf locked lvdrf avdf avdie reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x 1 st7lite1 34/131 8 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 19 . the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: ? normal processing is suspended at the end of the current instruction execution. ? the pc, x, a and cc registers are saved onto the stack. ? the i bit of the cc register is set to prevent addi- tional interrupts. ? the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which caus es the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt cannot be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the interrupt map- ping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifi- cally mentioned interrupts allow the processor to leave the halt low power mode (refer to the ?exit from halt? column in th e interrupt mapping ta- ble). 8.1 non maskable software interrupt this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced acco rding to the flowchart on figure 19 . 8.2 external interrupts external interrupt vectors can be loaded into the pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to le ave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt tr iggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. caution: the type of sensitivity defined in the mis- cellaneous or interrupt register (if available) ap- plies to the ei source. 8.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ? the i bit of the cc register is cleared. ? the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: ? writing ?0? to the corresponding bit in the status register or ? access to the status register while the flag is set followed by a read or write of an associated reg- ister. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed. 1 st7lite1 35/131 interrupts (cont?d) figure 19. interrupt processing flowchart table 5. interrupt mapping note 1 : this interrupt exits the mcu from ?auto wake-up from halt? mode only. n source block description register label priority order exit from halt or awufh exit from active -halt address vector reset reset n/a highest priority lowest priority yes yes fffeh-ffffh trap software interrupt no no fffch-fffdh 0 awu auto wake up interrupt awucsr yes 1) fffah-fffbh 1 ei0 external interrupt 0 n/a yes fff8h-fff9h 2 ei1 external interrupt 1 fff6h-fff7h 3 ei2 external interrupt 2 fff4h-fff5h 4 ei3 external interrupt 3 fff2h-fff3h 5 lite timer lite timer rtc2 interrupt ltcsr2 no fff0h-fff1h 6 not used ffeeh-ffefh 7 si avd interrupt sicsr no no ffech-ffedh 8 at timer at timer output compare interrupt or input capture interrupt pwmxcsr or atcsr ffeah-ffebh 9 at timer overflow interrupt atcsr yes ffe8h-ffe9h 10 lite timer lite timer input capture interrupt ltcsr no ffe6h-ffe7h 11 lite timer rtc1 interrupt ltcsr yes ffe4h-ffe5h 12 spi spi peripheral interrupts spicsr yes no ffe2h-ffe3h 13 not usednot used ffe0h-ffe1h i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending? 1 st7lite1 36/131 interrupts (cont?d) external interrupt control register (eicr) read/write reset value: 0000 0000 (00h) bit 7:6 = is3[1:0] ei3 sensitivity these bits define the interrupt sensitivity for ei3 (port b0) according to table 6 . bit 5:4 = is2[1:0] ei2 sensitivity these bits define the interrupt sensitivity for ei2 (port b3) according to table 6 . bit 3:2 = is1[1:0] ei1 sensitivity these bits define the interrupt sensitivity for ei1 (port a7) according to table 6 . bit 1:0 = is0[1:0] ei0 sensitivity these bits define the interrupt sensitivity for ei0 (port a0) according to table 6 . note: these 8 bits can be written only when the i bit in the cc register is set. table 6. interrupt sensitivity bits . external interrupt selection regis- ter (eisr) read/write reset value: 0000 1100 (0ch) bit 7:6 = ei3[1:0] ei3 pin selection these bits are written by software. they select the port b i/o pin used for the ei3 external interrupt ac- cording to the table below. external interrupt i/o pin selection * reset state bit 5:4 = ei2[1:0] ei2 pin selection these bits are written by software. they select the port b i/o pin used for the ei2 external interrupt ac- cording to the table below. external interrupt i/o pin selection * reset state 1) note that pb4 cannot be used as an external in- terrupt in halt mode. 70 is31 is30 is21 is20 is11 is10 is01 is00 isx1 isx0 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge 70 ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00 ei31 ei30 i/o pin 0 0 pb0 * 0 1 pb1 1 0 pb2 ei21 ei20 i/o pin 0 0 pb3 * 0 1 pb4 1) 1 0 pb5 1 1 pb6 1 st7lite1 37/131 interrupts (cont?d) bit 3:2 = ei1[1:0] ei1 pin selection these bits are written by software. they select the port a i/o pin used for the ei1 external interrupt ac- cording to the table below. external interrupt i/o pin selection * reset state bit 1:0 = ei0[1:0] ei0 pin selection these bits are written by software. they select the port a i/o pin used for the ei0 external interrupt ac- cording to the table below. external interrupt i/o pin selection * reset state bits 1:0 = reserved. ei11 ei10 i/o pin 0 0 pa4 0 1 pa5 1 0 pa6 1 1 pa7* ei01 ei00 i/o pin 0 0 pa0 * 0 1 pa1 1 0 pa2 1 1 pa3 1 st7lite1 38/131 9 power saving modes 9.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, five main pow- er saving modes are implemented in the st7 (see figure 20 ): slow wait (and slow-wait) active halt auto wake up from halt (awufh) halt after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency di vided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by callin g the specific st7 software instruction whose action depends on the oscillator status. figure 20. power saving mode transitions 9.2 slow mode this mode has two targets: ? to reduce power consumption by decreasing the internal clock in the device, ? to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by the sms bit in the mccsr register which enables or disables slow mode. in this mode, the oscillato r frequency is divided by 32. the cpu and peripherals are clocked at this lower frequency. note : slow-wait mode is activated when enter- ing wait mode while the device is already in slow mode. figure 21. slow mode clock transition power consumption wait slow run active halt high low slow wait auto wake up from halt halt sms f cpu normal run mode request f osc f osc /32 f osc 1 st7lite1 39/131 power saving modes (cont?d) 9.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i bit of the cc register is cleared, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the pro- gram counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wa it mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 22 . figure 22. wait mode flow-chart note: 1. before servicing an inte rrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals ibit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 0 on cpu oscillator peripherals ibit on on x 1) on cycle delay 256 or 4096 cpu clock 1 st7lite1 40/131 power saving modes (cont?d) 9.4 halt mode the halt mode is the lo west power consumption mode of the mcu. it is entered by executing the ?halt? instruction when active-halt is disabled (see section 9.5 on page 41 for more details) and when the awuen bit in the awucsr register is cleared. the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 5, ?interrupt mapping,? on page 35) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immedi ately turned on and the 256 or 4096 cpu cycle delay is used to stabilize the oscillator. afte r the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see fig- ure 24 ). when entering halt mode, the i bit in the cc reg- ister is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up im- mediately. in halt mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of wa tchdog operation with halt mode is configured by the ?wdghalt? op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see sec- tion 15.1 on page 121 for more details). figure 23. halt timing overview figure 24. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific inte rrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 5 interrupt mapping for more details. 4. before servicing an inte rrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when- the cc register is popped. 5. if the pll is enabled by option byte, it outputs the clock after a delay of t startup (see figure 11 ). halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [active halt disabled] reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off x 4) on cpu oscillator peripherals ibit on on x 4) on 256 or 4096 cpu clock delay 5) watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle halt instruction (active halt disabled) (awucsr.awuen=0) 1 st7lite1 41/131 power saving modes (cont?d) 9.4.1 halt mode recommendations ? make sure that an external event is available to wake up the microcontroller from halt mode. ? when using an external interrupt to wake up the microcontroller, reinitia lize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. ? for the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. ? the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in pro- gram memory with the value 0x8e. ? as the halt instruction clears the interrupt mask in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits be- fore executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corre- sponding to the wake-up event (reset or external interrupt). 9.5 active-halt mode active-halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the ?halt? in- struction. the decision to enter either in active- halt or halt mode is given by the ltcsr/atc- sr register status as shown in the following table: the mcu can exit active-halt mode on recep- tion of a specific interrupt (see table 5, ?interrupt mapping,? on page 35) or a reset. ? when exiting active-halt mode by means of a reset, a 256 or 4096 cpu cycle delay oc- curs. after the start up delay, the cpu resumes operation by fetching the reset vector which woke it up (see figure 26 ). ? when exiting active-halt mode by means of an interrupt, the cpu immediately resumes oper- ation by servicing the inte rrupt vector which woke it up (see figure 26 ). when entering active-halt mode, the i bit in the cc register is cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately (see note 3). in active-halt mode, on ly the main oscillator and the selected timer counter (lt/at) are running to keep a wake-up time base. all other peripherals are not clocked except those which get their clock supply from another clock generator (such as ex- ternal or auxiliary oscillator). note: as soon as active-halt is enabled, exe- cuting a halt instruction while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. ltcsr1 tb1ie bit atcsr ovfie bit atcsr ck1 bit atcsr ck0 bit meaning 0xx0 active-halt mode disabled 00xx 1 xxx active-halt mode enabled x 101 1 st7lite1 42/131 power saving modes (cont?d) figure 25. active-halt timing overview figure 26. active-halt mode flow-chart notes: 1. this delay occurs only if the mcu exits active- halt mode by means of a reset. 2. peripherals clocked with an external clock source can still be active. 3. only the rtc1 interrupt and some specific inter- rupts can exit the mcu from active-halt mode. refer to table 5, ?interrupt mapping,? on page 35 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 9.6 auto wake up from halt mode auto wake up from halt (awufh) mode is simi- lar to halt mode with the addition of a specific in- ternal rc oscillator for wake-up (auto wake up from halt oscillator). compared to active-halt mode, awufh has lower power consumption (the main clock is not kept running, but there is no ac- curate realtime clock available. it is entered by executing the halt instruction when the awuen bit in the awucsr register has been set. figure 27. awufh mode block diagram as soon as halt mode is entered, and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divid- er and a programmable prescaler controlled by the awupr register. the output of this prescaler pro- vides the delay time. when the delay has elapsed the awuf flag is set by hardware and an interrupt wakes-up the mcu from halt mode. at the same time the main oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. after this start-up delay, the cpu resumes oper- ation by servicing the awufh interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run mode. this connects f awu_rc to the input capture of the 12-bit auto-re- load timer, allowing the f awu_rc to be measured using the main oscillator cl ock as a reference time- base. halt run run 256 or 4096 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [active halt enabled] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals 2) ibit on off x 4) on cpu oscillator peripherals ibit on on x 4) on 256 or 4096 cpu clock delay (active halt enabled) (awucsr.awuen=0) cycle awu rc awufh f awu_rc awufh (ei0 source) oscillator prescaler/1 .. 255 interrupt /64 divider to timer input capture 1 st7lite1 43/131 power saving modes (cont?d) similarities with halt mode the following awufh mode behaviour is the same as normal halt mode: ? the mcu can exit awufh mode by means of any interrupt with exit from halt capability or a re- set (see section 9.4 halt mode ). ? when entering awufh mode, the i bit in the cc register is forced to 0 to enable interrupts. there- fore, if an interrupt is pending, the mcu wakes up immediately. ? in awufh mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. none of the peripherals are clocked except those which get their clock supply from another clock generator (such as an exte rnal or auxiliary oscil- lator like the awu oscillator). ? the compatibility of watchdog operation with awufh mode is configur ed by the wdghalt option bit in the option byte. depending on this setting, the halt instruction when executed while the watchdog system is enabled, can gen- erate a watchdog reset. figure 28. awuf halt timing diagram awufh interrupt f cpu run mode halt mode 256 or 4096 t cpu run mode f awu_rc clear by software t awu 1 st7lite1 44/131 power saving modes (cont?d) figure 29. awufh mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only an awufh interrup t and some specific in- terrupts can exit the mcu from halt mode (such as external interrupt). refer to table 5, ?interrupt mapping,? on page 35 for more details. 4. before servicing an inte rrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. 5. if the pll is enabled by option byte, it outputs the clock after an additional delay of t startup (see figure 11 ). reset interrupt 3) y n n y cpu main osc peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx 4) on cpu main osc peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock delay 5) watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle awu rc osc on awu rc osc off awu rc osc off halt instruction (active-halt disabled) (awucsr.awuen=1) 1 st7lite1 45/131 power saving modes (cont?d) 9.6.0.1 register description awufh control/status register (awucsr) read/write reset value: 0000 0000 (00h) bits 7:3 = reserved. bit 1= awuf auto wake up flag this bit is set by hardw are when the awu module generates an interrupt and cleared by software on reading awucsr. writing to this bit does not change its value. 0: no awu interrupt occurred 1: awu interrupt occurred bit 1= awum auto wake up measurement this bit enables the aw u rc oscillator and con- nects its output to the inputcapture of the 12-bit auto-reload timer. this allows the timer to be used to measure the awu rc oscillator disper- sion and then compensate this dispersion by pro- viding the right value in the awupre register. 0: measurement disabled 1: measurement enabled bit 0 = awuen auto wake up fr om halt enabled this bit enables the auto wake up from halt fea- ture: once halt mode is entered, the awufh wakes up the microcontroller after a time delay de- pendent on the awu prescaler value. it is set and cleared by software. 0: awufh (auto wake up from halt) mode disa- bled 1: awufh (auto wake up from halt) mode ena- bled awufh prescaler register (awupr) read/write bits 7:0= awupr[7:0] auto wake up prescaler these 8 bits define the awupr dividing factor (as explained below: in awu mode, the period that the mcu stays in halt mode (t awu in figure 28 on page 43 ) is de- fined by this prescaler register can be programmed to modify the time that the mcu stays in halt mode before waking up automatically. note: if 00h is written to awupr, depending on the product, an interrupt is generated immediately after a halt instruction, or the awupr remains inchanged. table 7. awu register map and reset values 70 00000 awu f awu m awu en 70 awu pr7 awu pr6 awu pr5 awu pr4 awu pr3 awu pr2 awu pr1 awu pr0 awupr[7:0 ] dividing factor 00h forbidden 01h 1 ... ... feh 254 ffh 255 t awu 64 awupr 1 f awurc ------------------------- -t rcstrt + = address (hex.) register label 76543210 0049h awupr reset value awupr7 1 awupr6 1 awupr5 1 awupr4 1 awupr3 1 awupr2 1 awupr1 1 awupr0 1 004ah awucsr reset value 00000awufawumawuen 1 st7lite1 46/131 10 i/o ports 10.1 introduction the i/o ports allow data transfer. an i/o port can contain up to 8 pins. each pin can be programmed independently either as a digital input or digital output. in addition, specific pins may have several other functions. these functions can include exter- nal interrupt, alternate signal input/output for on- chip peripherals or analog input. 10.2 functional description a data register (dr) and a data direction regis- ter (ddr) are always associated with each port. the option register (or) , which allows input/out- put options, may or may not be implemented. the following description take s into account the or register. refer to the port configuration table for device specific information. an i/o pin is programmed using the corresponding bits in the ddr, dr and or registers: bit x corre- sponding to pin x of the port. figure 30 shows the generic i/o block diagram. 10.2.1 input modes clearing the ddrx bit selects input mode. in this mode, reading its dr bit returns the digital value from that i/o pin. if an or bit is available, different input modes can be configured by software: floating or pull-up. re- fer to i/o port implementation section for configu- ration. notes : 1. writing to the dr modifies the latch value but does not change the state of the input pin. 2. do not use read/mod ify/write instructions (bset/bres) to modify the dr register. external interrupt function depending on the device, setting the orx bit while in input mode can configure an i/o as an input with interrupt. in this configuration, a signal edge or lev- el input on the i/o generates an interrupt request via the corresponding interrupt vector (eix). falling or rising edge sens itivity is programmed in- dependently for each interrupt vector. the exter- nal interrupt control register (eicr) or the miscel- laneous register controls this sensitivity, depend- ing on the device. external interrupts are hardware interrupts. fetch- ing the corresponding interrupt vector automatical- ly clears the request latch. modifying the sensitivity bits will clear any pending interrupts. 10.2.2 output modes setting the ddrx bit selects output mode. writing to the dr bits applies a digital value to the i/o through the latch. reading the dr bits returns the previously stored value. if an or bit is available, different output modes can be selected by software: push-pull or open- drain. refer to i/o port implementation section for configuration. dr value and output pin status 10.2.3 alternate functions many st7s i/os have one or more alternate func- tions. these may include output signals from, or input signals to, on-chip peripherals. the device pin description table describes which peripheral signals can be input/output to which ports. a signal coming from an on-chip peripheral can be output on an i/o. to do this, enable the on-chip peripheral as an output (enable bit in the peripher- al?s control register). the peripheral configures the i/o as an output and takes priority over standard i/ o programming. the i/o?s state is readable by ad- dressing the corresponding i/o data register. configuring an i/o as floating enables alternate function input. it is not recommended to configure an i/o as pull-up as this will increase current con- sumption. before using an i/o as an alternate in- put, configure it without interrupt. otherwise spuri- ous interrupts can occur. configure an i/o as input floating for an on-chip peripheral signal which can be input and output. caution : i/os which can be configured as both an analog and digital alternate function need special atten- tion. the user must control the peripherals so that the signals do not arrive at the same time on the same pin. if an external clock is used, only the clock alternate function should be employed on that i/o pin and not the other alternate function. dr push-pull open-drain 0v ol v ol 1v oh floating 1 st7lite1 47/131 i/o ports (cont?d) figure 30. i/o port general block diagram table 8. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note: the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ol is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external request (ei x ) interrupt sensitivity selection cmos schmitt trigger register access bit from on-chip periphera l to on-chip peripheral note : refer to the port configuration table for device specific information. combinational logic 1 st7lite1 48/131 i/o ports (cont?d) table 9. i/o configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate functi on output status. 2. when the i/o port is in output configuration and th e associated alternate function is enabled as an input, the alternate function reads the pin stat us given by the dr register content. 3. for true open drain, these elements are not implemented. hardware configuration input 1) open-drain output 2) push-pull output 2) note 3 condition pad v dd r pu external interrupt polarity data b u s pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register condition alternate input analog input to on-chip peripheral combinational logic note 3 pad r pu data bus dr dr register access r/w v dd register pad r pu data b u s dr dr register access r/w v dd alternate alternate enable output register bit from on-chip periphera l note 3 1 st7lite1 49/131 i/o ports (cont?d) analog alternate function configure the i/o as floating input to use an adc input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the adc input. analog recommendations do not change the voltage level or loading on any i/o while conversion is in progress. do not have clocking pins located close to a selected analog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 10.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific i/o port features such as adc input or open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 31 . other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation. figure 31. interrupt i/o port state transitions 10.4 unused i/o pins unused i/o pins must be connected to fixed volt- age levels. refer to section 13.8 . 10.5 low power modes 10.6 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and if the i bit in the cc register is cleared (rim instruction). mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or 1 st7lite1 50/131 i/o ports (cont?d) 10.7 device-specific i/o port configuration the i/o port register configurations are summa- rised as follows. standard ports pa7:0, pb6:0 interrupt ports ports where the external interrupt capability is selected using the eisr register table 10. port configuration (standard ports) note: on ports where the external inte rrupt capability is sele cted using the eisr r egister, the configura- tion will be as follows: table 11. i/o port register map and reset values mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:0 floating pull-up open drain push-pull port b pb6:0 floating pull-up open drain push-pull port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:0 floating pull-up interrupt open drain push-pull port b pb6:0 floating pull-up interrupt open drain push-pull address (hex.) register label 76543210 0000h padr reset value msb 1111111 lsb 1 0001h paddr reset value msb 0000000 lsb 0 0002h paor reset value msb 0100000 lsb 0 0003h pbdr reset value msb 1111111 lsb 1 0004h pbddr reset value msb 0000000 lsb 0 0005h pbor reset value msb 0000000 lsb 0 1 st7lite1 51/131 11 on-chip peripherals 11.1 watchdog timer (wdg) 11.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter?s contents before the t6 bit be- comes cleared. 11.1.2 main features programmable free-running downcounter (64 increments of 16000 cpu cycles) programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 11.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 16000 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low th e reset pin for typically 30s. figure 32. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 16000 t1 t2 t3 t4 t5 1 st7lite1 52/131 watchdog timer (cont?d) the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. this downcounter is free- running: it counts down even if the watchdog is disabled. the value to be stored in the cr register must be between ffh and c0h (see table 12 .watchdog timing ): ? the wdga bit is set (watchdog enabled) ? the t6 bit is set to prevent generating an imme- diate reset ? the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. table 12.watchdog timing notes: 1. the timing variation shown in table 12 is due to the unknown status of the prescaler when writing to the cr register. 2. the number of cpu clock cycles applied during the reset phase (256 or 4096) must be taken into account in addition to these timings. 11.1.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the option byte description in section 15 on page 121 . 11.1.4.1 using halt mode with the wdg (wdghalt option) if halt mode with watchdog is enabled by option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruc- tion to refresh the wdg counter, to avoid an unex- pected wdg reset immediately after waking up the microcontroller. same behavior in active-halt mode. f cpu = 8mhz wdg counter code min [ms] max [ms] c0h 1 2 ffh 127 128 1 st7lite1 53/131 watchdog timer (cont?d) 11.1.5 interrupts none. 11.1.6 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). 70 wdga t6 t5 t4 t3 t2 t1 t0 1 st7lite1 54/131 watchdog timer (cont?d) table 13. watchdog timer register map and reset values address (hex.) register label 76543210 002eh wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 1 st7lite1 55/131 11.2 12-bit autoreload timer 2 (at2) 11.2.1 introduction the 12-bit autoreload timer can be used for gen- eral-purpose timing functions. it is based on a free- running 12-bit upcounter with an input capture reg- ister and four pwm output channels. there are 6 external pins: ? four pwm outputs ? atic pin for the input capture function ? break pin for forcing a break condition on the pwm outputs 11.2.2 main features 12-bit upcounter with 12-bit autoreload register (atr) maskable overflow interrupt generation of four independent pwmx signals frequency 2khz-4mhz (@ 8 mhz f cpu ) ? programmable duty-cycles ? polarity control ? programmable output modes ? maskable compare interrupt input capture ? 12-bit input capture register (aticr) ? triggered by rising and falling edges ? maskable ic interrupt figure 33. block diagram atcsr cmpie ovfie ovf ck0 ck1 icie icf 0 12-bit autoreload register 12-bit upcounter cmpf2 cmpf1 cmpf3 cmpf0 cmp request ovf interrupt request f cpu atic 12-bit input capture register ic interrupt request atr aticr f counter cntr 32 mhz (1 ms f ltimer @ 8mhz) cmpfx bit pwm generation pol- arity opx bit pwmx comp- pare f pwm output control oex bit 4 pwm channels interrupt timebase dcr0h dcr0l preload preload on ovf event 12-bit duty cycle value (shadow) if tran=1 1 st7lite1 56/131 12-bit autoreload timer (cont?d) 11.2.3 functional description pwm mode this mode allows up to four pulse width modulat- ed signals to be generated on the pwmx output pins. the pwmx output signals can be enabled or disabled using the oex bits in the pwmcr regis- ter. pwm frequency and duty cycle the four pwm signals have the same frequency (f pwm ) which is controlled by the counter period and the atr register value. f pwm = f counter / (4096 - atr) following the above formula, ? if f counter is 32 mhz, the maximum value of f pwm is 8 mhz (atr register value = 4092), the minimum value is 8 khz (atr register value = 0) ? if f counter is 4 mhz , the maximum value of f pwm is 2 mhz (atr register value = 4094),the mini- mum value is 1 khz (atr register value = 0). note: the maximum value of atr is 4094 be- cause it must be lower than the dcr value which must be 4095 in this case. at reset, the counter starts counting from 0. when a upcounter overflow occurs (ovf event), the preloaded duty cycle values are transferred to the duty cycle registers and the pwmx signals are set to a high level. when the upcounter match- es the dcrx value the pwmx signals are set to a low level. to obtain a signal on a pwmx pin, the contents of the corresponding dcrx register must be greater than the contents of the atr register. the polarity bits can be used to invert any of the four output signals. the inversion is synchronized with the counter overflow if the tran bit in the trancr register is set (reset value). see figure 34 . figure 34. pwm inversion diagram the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (4096 - atr) note : to get the maximum resolution (1/4096), the atr register must be 0. with this maximum reso- lution, 0% and 100% can be obtained by changing the polarity. figure 35. pwm function pwmx pwmx pin counter overflow opx pwmxcsr register inverter dff tran trancr register duty cycle register auto-reload register pwmx output t 4095 000 with oe=1 and opx=0 (atr) (dcrx) with oe=1 and opx=1 counter 1 st7lite1 57/131 12-bit autoreload timer (cont?d) figure 36. pwm signal from 0% to 100% duty cycle output compare mode to use this function, load a 12-bit value in the dcrxh and dcrxl registers. when the 12-bit upcounter (cntr) reaches the value stored in the dcr xh and dcrxl registers, the cmpf bit in the pwmxcsr register is set and an interrupt request is generated if the cmpie bit is set. note: the output compare function is only availa- ble for dcrx values other than 0 (reset value). break function the break function is used to perform an emergen- cy shutdown of the power converter. the break function is activated by the external break pin (active low). in order to use the break pin it must be previo usly enabled by soft- ware setting the bpen bit in the breakcr regis- ter. when a low level is detected on the break pin, the ba bit is set and the break function is activat- ed. software can set the ba bit to activate the break function without using the break pin. when the break function is activated (ba bit =1): ? the break pattern (pwm[3:0] bits in the break- cr) is forced directly on the pwmx output pins (after the inverter). ? the 12-bit pwm counter is set to its reset value. ? the arr, dcrx and the corresponding shadow registers are set to their reset values. ? the pwmcr register is reset. when the break function is deactivated after ap- plying the break (ba bit goes from 1 to 0 by soft- ware): ? the control of pwm outputs is transferred to the port registers. counter pwmx output t with oex=1 and opx=0 ffdh ffeh fffh ffdh ffeh fffh ffdh ffeh dcrx=000h dcrx=ffdh dcrx=ffeh dcrx=000h atr= ffdh f counter pwmx output with oex=1 and opx=1 1 st7lite1 58/131 figure 37. block diagram of break function 11.2.3.1 input capture the 12-bit aticr register is used to latch the val- ue of the 12-bit free running upcounter after a ris- ing or falling edge is detected on the atic pin. when an input capture occurs, the icf bit is set and the aticr register contains the value of the free running upcounter. an ic interrupt is generat- ed if the icie bit is set. the icf bit is reset by read- ing the aticr register when the icf bit is set. the aticr is a read only register and always contains the free running upcounter value which corre- sponds to the most recent input capture. any fur- ther input capture is inhibited while the icf bit is set. figure 38. input capture timing diagram pwm0 pwm1 pwm2 pwm3 1 0 pwm0 pwm1 pwm2 pwm3 breakcr register break pin pwm counter -> reset value arr & dcrx -> reset value pwm mode -> reset value when ba is set: (active low) (inverters) note : the break pin value is latched by the ba bit. pwm0 pwm1 pwm2 pwm3 bpen ba counter t 01h f counter xxh 02h 03h 04h 05h 06h 07h 04h atic pin icf flag icr register interrupt 08h 09h 0ah interrupt aticr read 09h 1 st7lite1 59/131 12-bit autoreload timer (cont?d) 11.2.4 low power modes 11.2.5 interrupts note 1: the cmp and ic events are connected to the same interrupt vector. the ovf event is mapped on a separate vector (see interrupts chapter). they generate an interrupt if the enable bit is set in the atcsr register and the interrupt mask in the cc register is reset (rim instruction). note 2: only if ck0=1 and ck1=0 (f counter = f ltimer ) mode description slow the input frequency is divided by 32 wait no effect on at timer active-halt at timer halted except if ck0=1, ck1=0 and ovfie=1 halt at timer halted interrupt event 1) event flag enable control bit exit from wait exit from halt exit from active- halt overflow event ovf ovie yes no yes 2) ic event icf icie yes no no cmp event cmpf0 cmpie yes no no 1 st7lite1 60/131 12-bit autoreload timer (cont?d) 11.2.6 register description timer control status register (atcsr) read / write reset value: 0x00 0000 (x0h) bit 7 = reserved. bit 6 = icf input capture flag. this bit is set by hardware and cleared by software by reading the aticr register (a read access to aticrh or aticrl will clear this flag). writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred bit 5 = icie ic interrupt enable. this bit is set and cleared by software. 0: input capture interrupt disabled 1: input capture interrupt enabled bits 4:3 = ck[1:0] counter clock selection. these bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. note 1: pwm mode and output compare modes are not available at this frequency. note 2: aticr counter may return inaccurate re- sults when read. it is therefore not recommended to use input capture mode at this frequency. bit 2 = ovf overflow flag. this bit is set by hardware and cleared by software by reading the tcsr register. it indicates the tran- sition of the counter from fffh to atr value. 0: no counter overflow occurred 1: counter overflow occurred bit 1 = ovfie overflow interrupt enable. this bit is read/write by software and cleared by hardware after a reset. 0: ovf interrupt disabled. 1: ovf interrupt enabled. bit 0 = cmpie compare interrupt enable . this bit is read/write by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when the cmpf bit is set. 0: cmpf interrupt disabled. 1: cmpf interrupt enabled. counter register high (cntrh) read only reset value: 0000 0000 (000h) counter register low (cntrl) read only reset value: 0000 0000 (000h) bits 15:12 = reserved. bits 11:0 = cntr[11:0] counter value . this 12-bit register is read by software and cleared by hardware after a reset. the counter is incre- mented continuously as soon as a counter clok is selected. to obtain the 12-bit value, software should read the counter value in two consecutive read operations, lsb first. when a counter over- flow occurs, the counter restarts from the value specified in the atr register. 76 0 0 icf icie ck1 ck0 ovf ovfie cmpie counter clock selection ck1 ck0 off 0 0 f ltimer (1 ms timebase @ 8 mhz) 1) 01 f cpu 10 32 mhz 2) 11 15 8 0000 cntr 11 cntr 10 cntr9 cntr8 70 cntr7 cntr6 cntr5 cntr4 cntr3 cntr2 cntr1 cntr0 1 st7lite1 61/131 12-bit autoreload timer (cont?d) autoreload register (atrh) read / write reset value: 0000 0000 (00h) autoreload register (atrl) read / write reset value: 0000 0000 (00h) bits 11:0 = atr[11:0] autoreload register. this is a 12-bit register which is written by soft- ware. the atr register value is automatically loaded into the upcounter when an overflow oc- curs. the register value is used to set the pwm frequency. pwm output control register (pwmcr) read/write reset value: 0000 0000 (00h) bits 7:0 = oe[3:0] pwmx output enable . these bits are set and cleared by software and cleared by hardware after a reset. 0: pwm mode disabled. pwmx output alternate function disabled (i/o pin free for general pur- pose i/o) 1: pwm mode enabled pwmx control status register (pwmxcsr) read / write reset value: 0000 0000 (00h) bits 7:2= reserved, must be kept cleared. bit 1 = opx pwmx output polarity. this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the pwm signal. 0: the pwm signal is not inverted. 1: the pwm signal is inverted. bit 0 = cmpfx pwmx compare flag. this bit is set by hardware and cleared by software by reading the pwmxcsr register. it indicates that the upcounter value matches the dcrx regis- ter value. 0: upcounter value does not match dcr value. 1: upcounter value matches dcr value. break control register (breakcr) read/write reset value: 0000 0000 (00h) bits 7:6 = reserved. forced by hardware to 0. bit 5 = ba break active. this bit is read/write by software, cleared by hard- ware after reset and set by hardware when the break pin is low. it acti vates/deacti vates the break function. 0: break not active 1: break active 15 8 0 0 0 0 atr11 atr10 atr9 atr8 70 atr7 atr6 atr5 atr4 atr3 atr2 atr1 atr0 70 0oe30oe20oe10oe0 76 0 000000opxcmpfx 70 0 0 ba bpen pwm3 pwm2 pwm1 pwm0 1 st7lite1 62/131 12-bit autoreload timer (cont?d) bit 4 = bpen break pin enable. this bit is read/write by software and cleared by hardware after reset. 0: break pin disabled 1: break pin enabled bit 3:0 = pwm[3:0] break pattern. these bits are read/write by software and cleared by hardware after a reset. they are used to force the four pwmx output signals into a stable state when the break function is active. pwmx duty cycle register high (dcrxh) read / write reset value: 0000 0000 (00h) pwmx duty cycle register low (dcrxl) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved. bits 11:0 = dcr[11:0] pwmx duty cycle value this 12-bit value is wri tten by software. it defin- esthe duty cycle of the corresponding pwm output signal (see figure 35 ). in pwm mode (oex=1 in the pwmcr register) the dcr[11:0] bits define the duty cycle of the pwmx output signal (see figure 35 ). in output compare mode, they define the value to be com- pared with the 12-bit upcounter value. input capture register high (aticrh) read only reset value: 0000 0000 (00h) input capture register low (aticrl) read only reset value: 0000 0000 (00h) bits 15:12 = reserved. bits 11:0 = icr[11:0] input capture data . this is a 12-bit register which is readable by soft- ware and cleared by hardware after a reset. the aticr register contains captured the value of the 12-bit cntr register when a rising or falling edge occurs on the atic pin. capture will only be per- formed when the icf flag is cleared. transfer control register (trancr) read/write reset value: 0000 0001 (01h) bits 7:1 reserved. forced by hardware to 0. bit 0 = tran transfer enable this bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. it allows the value of the dcrx registers to be transferred to the dcrx shadow registers after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. 15 8 0 0 0 0 dcr11 dcr10 dcr9 dcr8 70 dcr7 dcr6 dcr5 dcr4 dcr3 dcr2 dcr1 dcr0 15 8 0 0 0 0 icr11 icr10 icr9 icr8 70 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 70 0000000tran 1 st7lite1 63/131 12-bit autoreload timer (cont?d) table 14. register map and reset values address (hex.) register label 76543210 0d atcsr reset value 0 icf 0 icie 0 ck1 0 ck0 0 ovf 0 ovfie 0 cmpie 0 0e cntrh reset value 0000 cntr11 0 cntr10 0 cntr9 0 cntr8 0 0f cntrl reset value cntr7 0 cntr8 0 cntr7 0 cntr6 0 cntr3 0 cntr2 0 cntr1 0 cntr0 0 10 atrh reset value 0000 atr11 0 atr10 0 atr9 0 atr8 0 11 atrl reset value atr7 0 atr6 0 atr5 0 atr4 0 atr3 0 atr2 0 atr1 0 atr0 0 12 pwmcr reset value 0 oe3 0 0 oe2 0 0 oe1 0 0 oe0 0 13 pwm0csr reset value 000000 op0 0 cmpf0 0 14 pwm1csr reset value 000000 op1 0 cmpf1 0 15 pwm2csr reset value 000000 op2 0 cmpf2 0 16 pwm3csr reset value 000000 op3 0 cmpf3 0 17 dcr0h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 18 dcr0l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 19 dcr1h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1a dcr1l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1b dcr2h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1c dcr2l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1d dcr3h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1e dcr3l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1f aticrh reset value 0000 icr11 0 icr10 0 icr9 0 icr8 0 20 aticrl reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 1 st7lite1 64/131 21 trancr reset value 0000000 tran 1 22 breakcr reset value 00 ba 0 bpen 0 pwm3 0 pwm2 0 pwm1 0 pwm0 0 address (hex.) register label 76543210 1 st7lite1 65/131 11.3 lite timer 2 (lt2) 11.3.1 introduction the lite timer can be used for general-purpose timing functions. it is based on two free-running 8- bit upcounters, an 8-bit input capture register. 11.3.2 main features realtime clock ? one 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 mhz f osc ) ? one 8-bit upcounter with autoreload and pro- grammable timebase period from 4s to 1.024ms in 4s increments (@ 8 mhz f osc ) ? 2 maskable timebase interrupts input capture ? 8-bit input capture register (lticr) ? maskable interrupt with wakeup from halt mode capability figure 39. lite timer 2 block diagram ltcsr1 8-bit timebase /2 8-bit f ltimer 8 ltic f osc /32 tb1f tb1ie tb icf icie lttb1 interrupt request ltic interrupt request lticr input capture register 1 0 1 or 2 ms timebase (@ 8mhz f osc ) to 12-bit at timer f ltimer ltcsr2 tb2f 0 tb2ie 0 lttb2 8-bit timebase 0 0 8-bit autoreload register 8 ltcntr ltarr counter 2 counter 1 0 0 interrupt request 1 st7lite1 66/131 lite timer (cont?d) 11.3.3 functional description 11.3.3.1 timebase counter 1 the 8-bit value of counter 1 cannot be read or written by software. after an mcu reset, it starts incrementing from 0 at a frequency of f osc /32. an overflow event occurs w hen the counter rolls over from f9h to 00h. if f osc = 8 mhz, then the time pe- riod between two counter overflow events is 1 ms. this period can be doubled by setting the tb bit in the ltcsr1 register. when counter 1 overflows, the tb1f bit is set by hardware and an interrupt request is generated if the tb1ie bit is set. the tb1f bit is cleared by software reading the ltcsr1 register. 11.3.3.2 timebase counter 2 counter 2 is an 8-bit autoreload upcounter. it can be read by accessing the ltcntr register. after an mcu reset, it increments at a frequency of f osc /32 starting from the value stored in the ltarr register. a counter overflow event occurs when the counter rolls over from ffh to the ltarr reload value. so ftware can write a new value at anytime in the ltarr register, this value will be automatically loade d in the counter when the next overflow occurs. when counter 2 overflows, the tb2f bit in the ltcsr2 register is set by hardware and an inter- rupt request is generated if the tb2ie bit is set. the tb2f bit is cleared by software reading the ltcsr2 register. 11.3.3.3 input capture the 8-bit input capture register is used to latch the free-running upcounter (counter 1) 1 after a rising or falling edge is detect ed on the ltic pin. when an input capture occurs, the icf bit is set and the lticr1 register contains the msb of counter 1. an interrupt is generated if the icie bit is set. the icf bit is cleared by reading the lticr register. the lticr is a read-only register and always con- tains the data from the last input capture. input capture is inhibited if the icf bit is set. figure 40. input capture timing diagram. 04h 8-bit counter 1 t 01h f osc /32 xxh 02h 03h 05h 06h 07h 04h ltic pin icf flag lticr register cleared 4s (@ 8mhz f osc ) f cpu by s/w 07h reading ltic register 1 st7lite1 67/131 lite timer (cont?d) ? the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. ? as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 11.3.4 low power modes 11.3.5 interrupts note: the tbxf and icf interrupt events are con- nected to separate interrupt vectors (see inter- rupts chapter). they generate an interrupt if the enable bit is set in the ltcsr1 or ltcsr2 register and the interrupt mask in the cc register is reset (rim instruction). 11.3.6 register description lite timer control/status register 2 (ltcsr2) read / write reset value: 0x00 0000 (x0h) bits 7:2 = reserved, mu st be kept cleared. bit 1 = tb2ie timebase 2 interrupt enable . this bit is set and cleared by software. 0: timebase (tb2) interrupt disabled 1: timebase (tb2) interrupt enabled bit 0 = tb2f timebase 2 interrupt flag . this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter 2 overflow 1: a counter 2 overflow has occurred lite timer auto reload register (ltarr) read / write reset value: 0000 0000 (00h) bits 7:0 = ar[7:0] counter 2 reload value. these bits register is read/write by software. the ltarr value is automatica lly loaded into counter 2 (ltcntr) when an overflow occurs. mode description slow no effect on lite timer (this peripheral is driven directly by f osc /32) wait no effect on lite timer active-halt no effect on lite timer halt lite timer stops counting interrupt event event flag enable control bit exit from wait exit from active halt exit from halt timebase 1 event tb1f tb1ie yes yes no timebase 2 event tb2f tb2ie yes no no ic event icf icie yes no no 70 000000tb2ietb2f 70 ar7 ar7 ar7 ar7 ar3 ar2 ar1 ar0 1 st7lite1 68/131 lite timer (cont?d) lite timer counter 2 (ltcntr) read only reset value: 0000 0000 (00h) bits 7:0 = cnt[7:0] counter 2 reload value. this register is read by software. the ltarr val- ue is automatically loaded into counter 2 (ltcn- tr) when an overflow occurs. lite timer control/status register (ltcsr1) read / write reset value: 0x00 0000 (x0h) bit 7 = icie interrupt enable. this bit is set and cleared by software. 0: input capture (ic) interrupt disabled 1: input capture (ic) interrupt enabled bit 6 = icf input capture flag. this bit is set by hardware and cleared by software by reading the lticr register. writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred note: after an mcu reset, so ftware must initialise the icf bit by reading the lticr register bit 5 = tb timebase period selection. this bit is set and cleared by software. 0: timebase period = t osc * 8000 (1ms @ 8 mhz) 1: timebase period = t osc * 16000 (2ms @ 8 mhz) bit 4 = tb1ie timebase interrupt enable . this bit is set and cleared by software. 0: timebase (tb1) interrupt disabled 1: timebase (tb1) interrupt enabled bit 3 = tb1f timebase interrupt flag . this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter overflow 1: a counter overflow has occurred bits 2:0 = reserved lite timer input capture register (lticr) read only reset value: 0000 0000 (00h) bits 7:0 = icr[7:0] input capture value these bits are read by software and cleared by hardware after a reset. if the icf bit in the ltcsr is cleared, the value of t he 8-bit up-counter will be captured when a rising or falling edge occurs on the ltic pin. 70 cnt7 cnt7 cnt7 cnt7 cnt3 cnt2 cnt1 cnt0 70 icie icf tb tb1ie tb1f - - - 70 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 1 st7lite1 69/131 lite timer (cont?d) table 15. lite timer register map and reset values address (hex.) register label 76543210 08 ltcsr2 reset value 000000 tb2ie 0 tb2f 0 09 ltarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 0a ltcntr reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 0b ltcsr1 reset value icie 0 icf x tb 0 tb1ie 0 tb1f 0 000 0c lticr reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 1 st7lite1 70/131 11.4 serial peripheral interface (spi) 11.4.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation six master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mode fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 general description figure 41 shows the serial peripheral interface (spi) block diagram. there are 3 registers: ? spi control register (spicr) ? spi control/status register (spicsr) ? spi data register (spidr) the spi is connected to external devices through 3 pins: ? miso: master in / slave out data ? mosi: master out / slave in data ? sck: serial clock out by spi masters and in- put by spi slaves ?ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves indi- vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand- ard i/o ports on the master device . figure 41. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 1 st7lite1 71/131 serial peripheral interface (cont?d) 11.4.3.1 functional description a basic example of inte rconnections between a single master and a sing le slave is illustrated in figure 42 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is alwa ys initiated by the mas- ter. when the master device transmits data to a slave device via mosi pin, the slave device re- sponds by sending data to the master device via the miso pin. this imp lies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node ( in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 45 ) but master and slave must be programmed with the same timing mode. figure 42. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software 1 st7lite1 72/131 serial peripheral interface (cont?d) 11.4.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis- ter (see figure 44 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ?ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 43 ): if cpha=1 (data latched on 2nd clock edge): ?ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag- ing the ss function by software (ssm= 1 and ssi=0 in the in the spicsr register) if cpha=0 (data latched on 1st clock edge): ?ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 11.4.5.3 ). figure 43. generic ss timing diagram figure 44. hardware/software slave select management mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin 1 st7lite1 73/131 serial peripheral interface (cont?d) 11.4.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). to operate the spi in master mode, perform the following steps in order (if the spicsr register is not written first, the spicr register setting (mstr bit ) may be not taken into account): 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 45 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: mstr and spe bits remain set only if ss is high. the transmit sequence begins when software writes a byte in the spidr register. 11.4.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig- nificant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. 11.4.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol- lowing actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 45 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in section 11.4.3.2 and figure 43 . if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to enable the spi i/o functions. 11.4.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig- nificant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spics r register while the spif bit is set. 2. a write or a read to the spidr register. notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 11.4.5.2 ). 1 st7lite1 74/131 serial peripheral interface (cont?d) 11.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 45 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 45 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. figure 45. data clock timing diagram sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3bit 2bit 1lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) 1 st7lite1 75/131 serial peripheral interface (cont?d) 11.4.5 error flags 11.4.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: ? the modf bit is set and an spi interrupt re- quest is generated if the spie bit is set. ? the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. ? the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig- inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multi master configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multi-master conflic t and allows software to handle this using an interrupt routine and either perform to a reset or return to an application de- fault state. 11.4.5.2 overrun condition (ovr) an overrun condition occurs, when the master de- vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: ? the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 11.4.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 11.4.3.2 slave select management . note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the cpu oper- ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 46 ). figure 46. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit result result 1 st7lite1 76/131 serial peripheral interface (cont?d) 11.4.5.4 single master and multimaster configurations there are two types of spi systems: ? single master system ? multimaster system single master system a typical single master system may be configured, using a device as the master and four device s as slaves (see figure 47 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previo us byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system ma y also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. figure 47. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave device slave device slave device slave device master device 1 st7lite1 77/131 serial peripheral interface (cont?d) 11.4.6 low power modes 11.4.6.1 using the spi to wake-up the device from halt mode in slave configuration, the spi is able to wake-up the device from halt mode through a spif inter- rupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to per- form an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake-up the device from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the device enters halt mode. so if slave se- lection is configured as external (see section 11.4.3.2 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 11.4.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events caus e the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper- ation resumes when the device is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from the spidr r egister when the soft- ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overru n error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of trans- fer event spif spie yes yes master mode fault event modf yes no overrun error ovr yes no 1 st7lite1 78/131 serial peripheral interface (cont?d) 11.4.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or over- run error occurs (spif=1, modf=1 or ovr=1 in the spicsr register) bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.4.5.1 master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not initia lly connected to the ex- ternal pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 16 spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.4.5.1 master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func- tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 16. spi master mode sck frequency 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 1 st7lite1 79/131 serial peripheral interface (cont?d) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr regist er. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. bit 6 = wcol write collision stat us (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 46 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 11.4.5.2 ). an interrupt is generated if spie = 1 in the spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 11.4.5.1 master mode fault (modf) ). an spi interrupt can be generated if spie=1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf=1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe=1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 11.4.3.2 slave select management . 0: hardware management (ss managed by exter- nal pin) 1: software management (internal ss signal con- trolled by ssi bit. external ss pin free for gener- al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will init iate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 41 ). 70 spif wcol ovr modf - sod ssm ssi 70 d7 d6 d5 d4 d3 d2 d1 d0 1 st7lite1 80/131 table 17. spi register map and reset values address (hex.) register label 76543210 0031h spidr reset value msb xxxxxxx lsb x 0032h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0033h spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0 1 st7lite1 81/131 11.5 10-bit a/d converter (adc) 11.5.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 7 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 7 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 11.5.2 main features 10-bit conversion up to 7 channels with multiplexed input linear successive approximation data register (dr) which contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 48 . 11.5.3 functional description 11.5.3.1 analog power supply v dda and v ssa are the high and low level refer- ence voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 48. adc block diagram ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 3 d1 d0 adcdrl 00 0 amp slow amp 0 r adc c adc hold control x 1 or x 8 ampsel bit sel f adc f cpu 0 1 1 0 div 2 div 4 slow bit cal 1 st7lite1 82/131 10-bit a/d converter (adc) (cont?d) 11.5.3.2 input voltage amplifier the input voltage can be amplified by a factor of 8 by enabling the ampsel bit in the adcdrl regis- ter. when the amplifier is enabled, the input range is 0v to v dd /8. for example, if v dd = 5v, then the adc can con- vert voltages in the range 0v to 430mv with an ideal resolution of 0.6mv (equivalent to 13-bit res- olution with reference to a v ss to v dd range). for more details, refer to the electrical character- istics section. note: the amplifier is switched on by the adon bit in the adccsr register, so no additional start- up time is required when the amplifier is selected by the ampsel bit. 11.5.3.3 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dda (high-level voltage reference) then the conversion result is ffh in the a dcdrh register and 03h in the adcdrl register (with out overflow indication). if the input voltage (v ain ) is lower than v ssa (low- level voltage reference) then the conversion result in the adcdrh and adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdrh and ad- cdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.5.3.4 a/d conversion the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: ? select the cs[2:0] bits to assign the analog channel to convert. adc conversion mode in the adccsr register: set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: ? the eoc bit is set by hardware. ? the result is in the adcdr registers. a read to the adcdrh resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll eoc bit 2. read adcdrl 3. read adcdrh. this clears eoc automati- cally. to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read adcdrh. this clears eoc automati- cally. 11.5.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed and between single shot conversions. 11.5.5 interrupts none. mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. 1 st7lite1 83/131 10-bit a/d converter (adc) (cont?d) 11.5.6 register description control/status register (adccsr) read/write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by soft- ware reading the adcdrh register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection this bit is set and cleared by software. it is used together with the slow bit to configure the adc clock speed. refer to the table in the slow bit de- scription. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter and amplifier are switched off 1: a/d converter and amplifier are switched on bit 4:3 = reserved. must be kept cleared. bit 2:0 = ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *the number of channels is device dependent. refer to the device pinout description. data register high (adcdrh) read only reset value: xxxx xxxx (xxh) bit 7:0 = d[9:2] msb of analog converted value amp control/data register low (ad- cdrl) read/write reset value: 0000 00xx (0xh) bit 7:5 = reserved. forced by hardware to 0. bit 4 = ampcal amplifier calibration bit this bit is set and cleared by software. user is sug- gested to use this bit to calibrate the adc when amplifier is on. setting th is bit internally connects amplifier input to 0v. hence, corresponding adc output can be used in software to eliminate ampli- fier-offset error. 0: calibration off 1: calibration on. (the input voltage of the amp is set to 0v) note: it is advised to use this bit to calibrate the adc when the amplifier is on. setting this bit in- ternally connects the amplifier input to 0v. hence, the corresponding adc output can be used in soft- ware to eliminate an amplifier-offset error. bit 3 = slow slow mode this bit is set and cleared by software. it is used together with the speed bi t to configure the adc clock speed as shown on the table below. 70 eoc speed adon 0 ch3 ch2 ch1 ch0 channel pin* ch2 ch1 ch0 ain0 0 0 0 ain1 0 0 1 ain2 0 1 0 ain3 0 1 1 ain4 1 0 0 ain5 1 0 1 ain6 1 1 0 70 d9 d8 d7 d6 d5 d4 d3 d2 70 000 amp cal slow amp- sel d1 d0 f adc slow speed f cpu /2 00 f cpu 01 f cpu /4 1x 1 st7lite1 84/131 bit 2 = ampsel amplifier selection bit this bit is set and cleared by software. 0: amplifier is not selected 1: amplifier is selected note: when ampsel=1 it is mandatory that f adc be less than or equal to 2 mhz. bit 1:0 = d[1:0] lsb of analog converted value table 18. adc register map and reset values address (hex.) register label 76543210 0034h adccsr reset value eoc 0 speed 0 adon 0 0 0 0 0 ch2 0 ch1 0 ch0 0 0035h adcdrh reset value d9 x d8 x d7 x d6 x d5 x d4 x d3 x d2 x 0036h adcdrl reset value 0 0 0 0 0 0 ampcal 0 slow 0 ampsel 0 d1 x d0 x 1 st7lite1 85/131 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: ? long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. ? short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 19. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10. w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) + 1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10] ,#7,skip 00..ff 00..ff byte + 3 1 st7lite1 86/131 st7 addressing modes (cont?d) 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 12.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, t hus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations 1 st7lite1 87/131 st7 addressing modes (cont?d) 12.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 20. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative 1 st7lite1 88/131 12.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 ma in groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. 12.2.1 illegal opcode reset in order to provide enhanced robustness to the de- vice against unexpected behaviour, a system of il- legal opcode detection is implemented. if a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. this, com- bined with the watchdog, allows the detection and recovery from an unexpected fault or interference. note: a valid prebyte associated with a valid op- code forming an unauthorized combination does not generate a reset. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf 1 st7lite1 89/131 instruction groups (cont?d) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine retu rn pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > 1 st7lite1 90/131 instruction groups (cont?d) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z 1 st7lite1 91/131 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v (for the 4.5v v dd 5.5v voltage range) and v dd =3.3v (for the 3v v dd 4v voltage range). they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 49 . figure 49. pin loading conditions 13.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 50 . figure 50. pin input voltage c l st7 pin v in st7 pin 1 st7lite1 92/131 13.2 absolute ma ximum ratings stresses above those listed as ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 13.2.1 voltage characteristics 13.2.2 current characteristics 13.2.3 thermal characteristics notes: 1. directly connecting the i/o pins to v dd or v ss could damage the device if an unexpec ted change of the i/o configura- tion occurs (for example, due to a co rrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-dow n resistor (typical: 10k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st7lite1 94/131 13.3.2 operating condi tions with low voltage detector (lvd) t a = -40 to 85c, unless otherwise specified note: 1. not tested in production. 2. not tested in production. the v dd rise time rate condition is needed to in sure a correct device power-on and lvd reset. when the v dd slope is outside these values, the lvd may not ensure a proper reset of the mcu. 13.3.3 auxiliary voltage detector (avd) thresholds t a = -40 to 85c, unless otherwise specified note: 1. not tested in production. 13.3.4 internal rc oscillator and pll the st7 internal clock can be supplie d by an internal rc oscillator and pll (selectable by option byte). symbol parameter conditions min typ max unit v it+ (lvd) reset release threshold (v dd rise) high threshold med. threshold low threshold 4.00 1) 3.40 1) 2.65 1) 4.25 3.60 2.90 4.50 3.80 3.15 v v it- (lvd) reset generation threshold (v dd fall) high threshold med. threshold low threshold 3.80 3.20 2.40 4.05 3.40 2.70 4.30 1) 3.65 1) 2.90 1) v hys lvd voltage threshold hysteresis v it+ (lvd) -v it- (lvd) 200 mv vt por v dd rise time rate 2) 20 20000 s/v t g(vdd) filtered glitch delay on v dd not detected by the lvd 150 ns i dd(lvd ) lvd/avd current consumption 220 a symbol parameter conditions min typ max unit v it+ (avd) 1=>0 avdf flag toggle threshold (v dd rise) high threshold med. threshold low threshold 4.40 1) 3.90 1) 3.20 1) 4.70 4.10 3.40 5.00 4.30 3.60 v v it- (avd) 0=>1 avdf flag toggle threshold (v dd fall) high threshold med. threshold low threshold 4.30 3.70 2.90 4.60 3.90 3.20 4.90 1) 4.10 1) 3.40 1) v hys avd voltage threshold hysteresis v it+ (avd) -v it- (avd) 150 mv ? v it- voltage drop between avd flag set and lvd reset activation v dd fall 0.45 v symbol parameter conditions min typ max unit v dd(rc) internal rc oscillator operating voltage 2.4 5.5 v v dd(x4pll) x4 pll operating voltage 2.4 3.3 v dd(x8pll) x8 pll operating voltage 3.3 5.5 t startup pll startup time 60 pll input clock (f pll ) cycles 1 st7lite1 95/131 operating conditions (cont?d) the rc oscillator and pll ch aracteristics are temperat ure-dependent a nd are grouped in four tables. 13.3.4.1 devices with ??6? order code suffix (tested for t a = -40 to +85c) @ v dd = 4.5 to 5.5v notes: 1. data based on characterization results, not tested in production 2. rccr0 is a factory-calibrated setting for 1000khz with 0.2 accuracy @ t a =25c, v dd =5v. see ?internal rc os- cillator adjustment? on page 23 3. guaranteed by design. 4. averaged over a 4ms period. after t he locked bit is set, a period of t stab is required to reach acc pll accuracy. 5. after the locked bit is set acc pll is max. 10% until t stab has elapsed. see figure 11 on page 24 . symbol parameter conditions min typ max unit f rc internal rc oscillator fre- quency rccr = ff (reset value), t a =25c,v dd =5v 760 khz rccr = rccr0 2 ) ,t a =25c,v dd =5v 1000 acc rc accuracy of internal rc oscillator with rccr=rccr0 2) t a =25c,v dd =4.5 to 5.5v -1 + 1% t a =-40 to +85c,v dd =5v -5 +2 % t a =0 to +85c,v dd =4.5 to 5.5v -2 1) +2 1) % i dd(rc) rc oscillator current con- sumption t a =25c,v dd =5v 970 1) a t su(rc) rc oscillator setup time t a =25c,v dd =5v 10 2) s f pll x8 pll input clock 1 1) mhz t lock pll lock time 5) 2ms t stab pll stabilization time 5) 4ms acc pll x8 pll accuracy f rc = 1mhz@t a =25c,v dd =4.5 to 5.5v 0.1 4) % f rc = 1mhz@t a =-40 to +85c,v dd =5v 0.1 4) % t w(jit) pll jitter period f rc = 1mhz 8 3) khz jit pll pll jitter ( ? f cpu /f cpu )1 3) % i dd(pll) pll current consumption t a =25c 600 1) a 1 st7lite1 96/131 operating conditions (cont?d) 13.3.4.2 devices with ??6? order code suffix (tested for t a = -40 to +85c) @ v dd = 2.7 to 3.3v notes: 1. data based on characterization results, not tested in production 2. rccr1 is a factory-calibrated setting for 700mhz with 0.2 accuracy @ t a =25c, v dd =3v. see ?internal rc os- cillator adjustment? on page 23. 3. guaranteed by design. 4. averaged over a 4ms period. after t he locked bit is set, a period of t stab is required to reach acc pll accuracy 5. after the locked bit is set acc pll is max. 10% until t stab has elapsed. see figure 11 on page 24 . symbol parameter conditions min typ max unit f rc internal rc oscillator fre- quency rccr = ff (reset value), t a =25c, v dd = 3.0v 560 khz rccr=rccr1 2) ,t a =25c,v dd = 3v 700 acc rc accuracy of internal rc oscillator when calibrated with rccr=rccr1 1)2) t a =25c,v dd =3v -2 +2 % t a =25c,v dd =2.7 to 3.3v -25 +25 % t a =-40 to +85c,v dd =3v -15 15 % i dd(rc) rc oscillator current con- sumption t a =25c,v dd =3v 700 1) a t su(rc) rc oscillator setup time t a =25c,v dd =3v 10 2) s f pll x4 pll input clock 0.7 1) mhz t lock pll lock time 5) 2ms t stab pll stabilization time 5) 4ms acc pll x4 pll accuracy f rc = 1mhz@t a =25c,v dd =2.7 to 3.3v 0.1 4) % f rc = 1mhz@t a =40 to +85c,v dd = 3v 0.1 4) % t w(jit) pll jitter period f rc = 1mhz 8 3) khz jit pll pll jitter ( ? f cpu /f cpu )1 3) % i dd(pll) pll current consumption t a =25c 190 1) a 1 st7lite1 97/131 operating conditions (cont?d) figure 52. rc osc freq vs v dd @ t a =25c (calibrated with rccr1: 3v @ 25c) figure 53. rc osc freq vs v dd (calibrated with rccr0: 5v@ 25c) figure 54. typical rc oscillator accuracy vs temperature @ v dd =5v (calibrated with rccr0: 5v @ 25c figure 55. rc osc freq vs v dd and rccr value 0.50 0.60 0.70 0.80 0.90 1.00 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 v dd ( v ) output freq (mhz ) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 2.533.544.555.56 vdd (v) output freq. (mhz) -45 0 25 90 105 130 2 -1 -5 -45 025 85 -2 -4 -3 0 1 ( * ) ( * ) ( * ) ( * ) tested in production temperature (c) rc accuracy 125 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.4 2.7 3 3.3 3.75 4 4.5 5 5.5 6 vdd (v) output freq. (mhz) rccr=00h rccr=64h rccr=80h rccr=c0h rccr=ffh 1 st7lite1 98/131 operating conditions (cont?d) figure 56. pll ? f cpu /f cpu versus time figure 57. pllx4 output vs clkin frequency note: f osc = f clkin /2*pll4 figure 58. pllx8 output vs clkin frequency note: f osc = f clkin /2*pll8 13.3.4.3 32mhz pll t a = -40 to 85c, unless otherwise specified note 1: 32 mhz is guaranteed within this voltage range. t w(jit) ? f cpu /f cpu t min max 0 t w(jit) 1.00 2.00 3.00 4.00 5.00 6.00 7.00 11.522.53 external input clock frequency (mhz) output frequency (mhz) 3.3 3 2.7 1.00 3.00 5.00 7.00 9.00 11.00 0.85 0.9 1 1.5 2 2.5 external input clock frequency (mhz) output frequency (mhz) 5.5 5 4.5 4 symbol parameter min typ max unit v dd voltage 1) 4.5 5 5.5 v f pll32 frequency 1) 32 mhz f input input frequency 7 89mhz 1 st7lite1 99/131 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). 13.4.1 supply current t a = -40 to +85c unless otherwise specified, v dd =5.5v notes: 1. cpu running with memory access, all i/o pi ns in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driv en by external square wave, lvd disabled. 2. all i/o pins in input m ode with a static value at v dd or v ss (no load), all peripherals in re set state; clock input (clkin) driven by external square wave, lvd disabled. 3. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in i nput mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripher als in reset state; clock input (clkin) dr iven by external square wave, lvd disabled. 5. all i/o pins in output m ode with a static value at v ss (no load), lvd disabl ed. data based on characterization results, tested in production at v dd max and f cpu max. 6. all i/o pins in input m ode with a static value at v dd or v ss (no load). data tested in production at v dd max. and f cpu max. 7. this consumption refers to the halt period only and not t he associated run period which is software dependent. figure 59. typical i dd in run vs. f cpu figure 60. typical i dd in slow vs. f cpu symbol parameter conditions typ max unit i dd supply current in run mode external clock, f cpu =1mhz 1) 1 ma internal rc, f cpu =1mhz 2.2 f cpu =8mhz 1) 7.5 12 supply current in wait mode external clock, f cpu =1mhz 2) 0.8 internal rc, f cpu =1mhz 1.8 f cpu =8mhz 2) 3.7 6 supply current in slow mode f cpu =250khz 3) 1.6 2.5 supply current in slow wait mode f cpu =250khz 4) 1.6 2.5 supply current in halt mode 5) -40c t a +85c 110 a t a = +125c 15 50 supply current in awufh mode 6)7) t a = +25c 20 30 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 2.02.53.03.54.04.55.05.56.0 vdd (v) idd (ma) 8mhz 4mhz 1mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd (v) idd (ma) 250khz 125khz 62.5hz 1 st7lite1 100/131 supply current characterisitcs (cont?d) figure 61. typical i dd in wait vs. f cpu figure 62. typical i dd in slow-wait vs. f cpu figure 63. typical i dd in awufh mode at t a =25c figure 64. typical i dd vs. temperature at v dd = 5v and f cpu = 8mhz 13.4.2 on-chip peripherals 1. data based on a differential i dd measurement between reset configuration (timer stopped) and a timer running in pwm mode at f cpu =8mhz. 2. data based on a differential i dd measurement between reset configurati on and a permanent spi master communica- tion (data sent equal to 55h). 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions with am- plifier off. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) idd (ma) 8mhz 4mhz 1mhz tbd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) idd (ma) 250khz 125khz 62.5khz 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd(v) idd(ma) fawu_rc ~125 khz 2.0 3.0 4.0 5.0 6.0 7.0 8.0 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 vdd (v) idd (ma) 25 -45 90 130 symbol parameter conditions typ unit i dd(at) 12-bit auto-reload timer supply current 1) f cpu =4mhz v dd = 3.0v 300 a f cpu =8mhz v dd = 5.0v 1000 i dd(spi) spi supply current 2) f cpu =4mhz v dd = 3.0v 50 f cpu =8mhz v dd = 5.0v 300 i dd(adc) adc supply current when converting 3) f adc =4mhz v dd = 3.0v 250 v dd = 5.0v 1100 1 st7lite1 101/131 13.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . 13.5.1 general timings notes: 1. guaranteed by design. not tested in production. 2. data based on typical application software. 3. time measured between interrupt event and interrupt vector fetch. dt c(inst) is the number of t cpu cycles needed to fin- ish the current instruction execution. 13.5.2 auto wakeup from halt oscillator (awu) symbol parameter 1) conditions min typ 2) max unit t c(inst) instruction cycle time f cpu =8mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time 3) t v(it) = ? t c(inst) + 10 f cpu =8mhz 10 22 t cpu 1.25 2.75 s symbol parameter conditions min typ max unit f awu awu oscillator frequency 50 125 250 khz t rcsrt awu oscillator startup time 50 s 1 st7lite1 102/131 13.6 memory characteristics t a = -40c to 85c, unless otherwise specified 13.6.1 ram and hardware registers 13.6.2 flash program memory 13.6.3 eeprom data memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). guaranteed by construction, not tested in production. 2. up to 32 bytes can be programmed at a time. 3. the data retention time increases when the t a decreases. 4. data based on reliability test results and monitored in production. 5. data based on characterization results, not tested in production. 6. guaranteed by design. not tested in production. 7. design target value pending fu ll product characterization. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditions min typ max unit v dd operating voltage for flash write/erase 2.4 5.5 v t prog programming time for 1~32 bytes 2) t a =? 40 to +85c 5 10 ms programming time for 1.5 kbytes t a = +25c 0.24 0.48 s t ret data retention 4) t a = +55c 3) 20 years n rw write erase cycles t a = +25c 10k 7) cycles i dd supply current read / write / erase modes f cpu = 8mhz, v dd = 5.5v 2.6 6) ma no read/no write mode 100 a power down mode / halt 0 0.1 a symbol parameter conditions min typ max unit v dd operating voltage for eeprom write/erase 2.4 5.5 v t prog programming time for 1~32 bytes t a =? 40 to +85c 5 10 ms t ret data retention 4) t a =+55c 3) 20 years n rw write erase cycles t a = +25c 300k 7) cycles st7lite1 103/131 13.7 emc characteristics susceptibility tests are pe rformed on a sample ba- sis during product characterization. 13.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test confor ms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. the test results are given in the table be- low based on the ems levels and classes defined in application note an1709. 13.7.1.1 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). 13.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/ 3 which specifies the board and the loading of each pin. notes: 1. data based on characterization results, not tested in production. symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 3b v fftb fast transient voltage bur st limits to be applied through 100pf on v dd and v dd pins to induce a func- tional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 3b symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 8/4mhz 16/8mhz s emi peak level v dd = 5v, t a = +25c, so20 package, conforming to sae j 1752/3 0.1mhz to 30mhz 9 17 db v 30mhz to 130mhz 31 36 130mhz to 1ghz 25 27 sae emi level 3.5 4 - st7lite1 104/131 emc characteristics (cont?d) 13.7.3 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measuremen t methods, the product is stressed in order to determine its performance in terms of electrical sensitiv ity. for more details, re- fer to the application note an1181. 13.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22- a114a/a115a standard. absolute maximum ratings notes: 1. data based on characterization results, not tested in production. 13.7.3.2 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1 000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities notes: 1. class description: a class is an stmicr oelectronics internal specif ication. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standar d. b class strictly covers all the jedec criteria (int ernational standard). symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 4000 v symbol parameter conditions class 1) lu static latch-up class t a = +25c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a st7lite1 105/131 13.8 i/o port pin characteristics 13.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. notes: 1. data based on characterization results, not tested in production. 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using t he output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 65 ). data based on design simulation and/or technology characteristics, not tested in production. 3. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- scribed in figure 66 ). 4. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. figure 65. two typical applications with unused i/o pin figure 66. typical i pu vs. v dd with v in =v ss symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3xv dd v v ih input high level voltage 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis 1) 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption 2) floating input mode 200 r pu weak pull-up equivalent resistor 3) v in = v ss v dd =5v 50 120 250 k ? v dd =3v 160 c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time 1) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 1) 25 t w(it)in external interrupt pulse time 4) 1t cpu 10k ? unused i/o port st7xxx 10k ? unused i/o port st7xxx v dd caution : during normal operation the iccclk pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in this is to avoid entering icc mode unexpectedly during a reset. noisy environment). to be characterized 0 10 20 30 40 50 60 70 80 90 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) ipu(ua) ta=140c ta=95c ta=25c ta=-45c st7lite1 106/131 i/o port pin characteristics (cont?d) 13.8.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. notes: 1. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . 3. not tested in production, based on characterization results. figure 67. typical v ol at v dd =2.4v (standard) figure 68. typical v ol at v dd =2.7v (standard) symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 70 ) v dd =5v i io =+5ma t a 85c t a 85c 1.0 1.2 v i io =+2ma t a 85c t a 85c 0.4 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 72 ) i io =+20ma, t a 85c t a 85c 1.3 1.5 i io =+8ma t a 85c t a 85c 0.75 0.85 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 78 ) i io =-5ma, t a 85c t a 85c v dd -1.5 v dd -1.6 i io =-2ma t a 85c t a 85c v dd -0.8 v dd -1.0 v ol 1)3) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 69 ) v dd =3.3v i io =+2ma t a 85c t a 85c 0.5 0.6 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io =+8ma t a 85c t a 85c 0.5 0.6 v oh 2)3) output high level voltage for an i/o pin when 4 pins are sourced at same time i io =-2ma t a 85c t a 85c v dd -0.8 v dd -1.0 v ol 1)3) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 68 ) v dd =2.7v i io =+2ma t a 85c t a 85c 0.6 0.7 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io =+8ma t a 85c t a 85c 0.6 0.7 v oh 2)3) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 75 ) i io =-2ma t a 85c t a 85c v dd -0.9 v dd -1.0 to be characterized 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.01 1 2 lio (ma) vol at vdd=2.4v -45 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.01 1 2 lio (ma) vol at vdd=2.7v -45c 0c 25c 90c 130c st7lite1 107/131 i/o port pin characteristics (cont?d) figure 69. typical v ol at v dd =3.3v (standard) figure 70. typical v ol at v dd =5v (standard) figure 71. typical v ol at v dd =2.4v (high-sink) figure 72. typical v ol at v dd =5v (high-sink) figure 73. typical v ol at v dd =3v (high-sink) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.01 1 2 3 lio (ma) vol at vdd=3.3v -45c 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.0112345 lio (ma) vol at vdd=5v -45c 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 678910 lio (ma) vol at vdd=2.4v (hs) -45 0c 25c 90c 130c 0.00 0.50 1.00 1.50 2.00 2.50 6 7 8 9 10 15 20 25 30 35 40 lio (ma) -45 0c 25c 90c 130c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 67891015 lio (ma) vol (v) at vdd=3v (hs) -45 0c 25c 90c 130c st7lite1 108/131 i/o port pin characteristics (cont?d) figure 74. typical v dd -v oh at v dd =2.4v figure 75. typical v dd -v oh at v dd =2.7v figure 76. typical v dd -v oh at v dd =3v figure 77. typical v dd -v oh at v dd =4v figure 78. typical v dd -v oh at v dd =5v 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 -0.01 -1 -2 lio (ma) vdd-voh at vdd=2.4v -45c 0c 25c 90c 130c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -0.01 -1 -2 lio(ma) vdd-voh at vdd=2.7v -45c 0c 25c 90c 130c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 -0.01-1-2-3 lio (ma) vdd-voh at vdd=3v -45c 0c 25c 90c 130c 0.00 0.50 1.00 1.50 2.00 2.50 -0.01-1-2-3-4-5 lio (ma) vdd-voh at vdd=4v -45c 0c 25c 90c 130c to be characterized 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 -0.01-1-2-3-4-5 lio (ma) vdd-voh at vdd=5v -45c 0c 25c 90c 130c st7lite1 109/131 i/o port pin characteristics (cont?d) figure 79. typical v ol vs. v dd (standard i/os) figure 80. typical v ol vs. v dd (high-sink i/os) figure 81. typical v dd -v oh vs. v dd 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 2.4 2.7 3.3 5 vdd (v) vol (v) at lio=2ma -45 0c 25c 90c 130c 0.00 0.01 0.02 0.03 0.04 0.05 0.06 2.4 2.7 3.3 5 vdd (v) vol (v) at lio=0.01ma -45 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 2.4 3 5 vdd (v) vol vs vdd (hs) at lio=8ma -45 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 2.4 3 5 vdd (v) vol vs vdd (hs) at lio=20ma -45 0c 25c 90c 130c 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 2.42.7345 vdd (v) vdd-voh (v) at lio=-2ma -45c 0c 25c 90c 130c 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 45 vdd vdd-voh at lio=-5ma -45c 0c 25c 90c 130c st7lite1 110/131 13.9 control pin characteristics 13.9.1 asynchronous reset pin t a = -40c to 85c, unless otherwise specified notes: 1. data based on characterization results, not tested in production. 2. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vss . 3. the r on pull-up equivalent resistor is based on a resistiv e transistor. specified for voltages on reset pin between v ilmax and v dd 4. to guarantee the reset of the device, a mi nimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3xv dd v v ih input high level voltage 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis 1) 2v v ol output low level voltage 2) v dd =5v i io =+5ma t a 85c t a 85c 0.5 1.0 1.2 v i io =+2ma t a 85c t a 85c 0.2 0.4 0.5 r on pull-up equivalent resistor 3) 1) v dd =5v 20 40 80 k ? v dd =3v. 40 70 120 t w(rstl)out generated reset pulse duration internal reset sources 30 s t h(rstl)in external reset pulse hold time 4) 20 s t g(rstl)in filtered glitch duration 200 ns st7lite1 111/131 control pin characteristics (cont?d) figure 82. reset pin protection when lvd is enabled. 1)2)3)4)5) figure 83. reset pin protection when lvd is disabled. 1)2)3) 1. the reset network protects t he device against parasitic resets. 2. the output of the external reset circuit must have an open-dr ain output to drive the st7 re set pad. otherwise the device can be damaged when the st7 generates an in ternal reset (lvd or watchdog). 3. whatever the reset source is (i nternal or external ), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 13.9.1 on page 110 . otherwise the reset will not be taken into account internally. 4. because the reset circuit is designed to allo w the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-up for example) is less than the absolute maximum value specified for i inj(reset) in section 13.2.2 on page 92 . 5. when the lvd is enabled, it is mandatory not to to connect a pull-up resistor and a capacitor to v dd on the reset pin . 0.01 f st72xxx pulse generator filter r on v dd watchdog lvd reset internal reset reset external recommended 0.01 f v dd 0.01 f external reset circuit user v dd 4.7k ? required recommended st72xxx pulse generator filter r on v dd watchdog internal reset st7lite1 112/131 13.10 communication interface characteristics 13.10.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). figure 84. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or charac terisation results, not tested in production. 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditions min max unit f sck = 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 = 0.0625 f cpu /4 = 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) ss setup time slave 120 ns t h(ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in st7lite1 113/131 communication interface characteristics (cont?d) figure 85. spi slave timing diagram with cpha=1 1) figure 86. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in seenote2 seenote2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) st7lite1 114/131 13.11 10-bit adc characteristics subject to general operating condition for v dd , f osc , and t a unless otherwise specified. figure 87. typical application with adc notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss . 3. any added external serial resist or will downgrade the adc accuracy (es pecially for resistance greater than 10k ? ). data based on characterization resu lts, not tested in production. 4. the stabilization time of the ad converter is masked by the fi rst t load . the first conversion after the enable is then always valid. symbol parameter conditions min typ 1) max unit f adc adc clock frequency 4 mhz v ain conversion voltage range 2) v ssa v dda v r ain external input resistor 10 3) k ? c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 4) s t adc conversion time (sample+hold) 3.5 - sample capacitor loading time - hold conversion time 4 10 1/f adc i adc analog part 1 ma digital part 0.2 ainx st72xxx v dd i l 1 a v t 0.6v v t 0.6v c adc 6pf v ain r ain 10-bit a/d conversion c ain st7lite1 115/131 adc characteristics (cont?d) adc accuracy with v dd =5.0v notes: 1) data based on characterization results over the whole temperature range, monitored in production. 2) injecting negative current on any of the analog input pins significantly reduc es the accuracy of any conversion being performed on any analog input. analog pins can be protected agai nst negative injection by adding a schottky diode (pin to ground). injecting negative current on digital input pins degrades adc accuracy especially if perform ed on a pin close to the analog input pins. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 13.8 does not affect the adc accuracy. figure 88. adc accuracy characteristics with amplifier disabled symbol parameter conditions typ max unit | e t | total unadjusted error 2) f cpu =8mhz, f adc =4mhz 1) , v dd =5.0v 36 lsb | e o | offset error 2) 1.5 5 | e g | gain error 2) 24.5 | e d | differential li nearity error 2) 2.5 4.5 | e l | integral linearity error 2) 2.5 4.5 e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dd v ss st7lite1 116/131 adc characteristics (cont?d) figure 89. adc accuracy characteristics with amplifier enabled note: when the ampsel bit in the adcdrl register is set, it is mandatory that f adc be less than or equal to 2 mhz. (if f cpu =8mhz. then speed=0, slow=1). e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted erro r: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 704 108 0 1234567 701 702 703 704 (1) (2) e t e d e l (3) v ss 430mv 62.5mv v in (opamp) vin vout (adc input) vmax vmin 430mv 0v noise (opamp input) st7lite1 117/131 adc characteristics (cont?d) notes: 1) data based on characterization results over t he whole temperature range, not tested in production. 2) for precise conversion results it is recommended to calibrate the amplifier at the following two points: ? offset at v inmin = 0v ? gain at full scale (for example v in =430mv) 3) monotonicity guaranteed if v in increases or decreases in steps of min. 5mv. 4) please refer to the application note an1830 for details of te% vs vin. 5) refer to the offset vari ation in temperature below amplifier output offset variation the offset is quite sensitive to temperature varia- tions. in order to ensure a good reliability in meas- urements, the offset must be recalibrated periodi- cally i.e. during power on or whenever the device is reset depending on the customer application and during temperature variation. the table below gives the typical offset variation over temperature: symbol parameter conditions min typ max unit v dd(amp) amplifier operating voltage 3.6 5.5 v v in amplifier input voltage 4) v dd =3.6v 0 350 mv v dd =5v 0 500 v offset amplifier output offset voltage 5) v dd =5v 200 mv v step step size for monotonicity 3) v dd =3.6v 3.5 mv v dd =5v 4.89 linearity output voltage response linear gain factor amplified analog input gain 2) 8 vmax output linearity max voltage v inmax = 430mv, v dd =5v 3.65 3.94 v vmin output linearity min voltage 200 mv typical offset variation (lsb) unit -45 -20 +25 +90 c -12 -7 - +13 lsb st7lite1 118/131 14 package characteristics 14.1 package mechanical data figure 90. 20-pin plastic small outline package, 300-mil width dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.60 13.00 0.496 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 20 eh a a1 b e d c h x 45 l a st7lite1 119/131 package characteristics (cont?d) table 21. thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipati on determined by the user. 2. the average chip-junction temperatur e can be obtained from the formula t j = t a + p d x rthja. symbol ratings value unit r thja package thermal resistance so20 (junction to ambient) dip20 125 tbd c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c st7lite1 120/131 14.2 soldering and glueability information recommended soldering information gi ven only as design guidelines. figure 91. recommended wave soldering profile (with 37% sn and 63% pb) figure 92. recommended reflow soldering oven profile (mid jedec) recommended glue for smd plastic packages: heraeus: pd945, pd955 loctite: 3615, 3298 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [c] ramp up 2c/sec for 50sec 90 sec at 125c 150 sec above 183c ramp down natural 2c/sec max tmax=220+/-5c for 25 sec st7lite1 121/131 15 device configuration each device is available for production in user pro- grammable versions (flash). st7flite1 devices are shipped to customers with a default program memory content (ffh). this implies that flash devices have to be con- figured by the customer using the option bytes . 15.1 option bytes the two option bytes allow the hardware configu- ration of the microcontroller to be selected. the option bytes can be accessed only in pro- gramming mode (for example using a standard st7 programming tool). option byte 0 opt7 = reserved, must always be 1. opt6:4 = oscrange[2:0] oscillator range when the internal rc osc illator is not selected (option osc=1), these option bits select the range of the resonator oscillator current source or the ex- ternal clock source. note: when the internal rc oscillator is selected, the oscrange option bits must be kept at their default value in order to select the 256 clock cycle delay (see section 7.5 ). opt3:2 = sec[1:0] sector 0 size definition these option bits indicate the size of sector 0 ac- cording to the following table. opt1 = fmp_r read-out protection readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to flash memory. erasing the option bytes when the fmp_r option is selected will cause the whole memory to be erased first and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.5 on page 14 for more de- tails 0: read-out protection off 1: read-out protection on opt0 = fmp_w flash write protection this option indicates if the flash program mem- ory is write protected. warning: when this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: write protection off 1: write protection on oscrange 210 typ. frequency range with resonator lp 1~2mhz 0 0 0 mp 2~4mhz 0 0 1 ms 4~8mhz 0 1 0 hs 8~16mhz 0 1 1 vlp 32.768khz 1 0 0 external clock source: clkin on osc1 1 0 1 on pb4 1 1 1 reserved 1 1 0 sector 0 size sec1 sec0 0.5k 00 1k 01 2k 10 4k 11 option byte 0 70 option byte 1 70 res. oscrange 2:0 sec1 sec0 fmp r fmp w pll x4x8 pll off pll32 off osc lvd1 lvd0 wdg sw wdg halt default value 11111 100 1 1 1 01111 st7lite1 122/131 option bytes (cont?d) option byte 1 opt7 = pllx4x8 pll factor selection. 0: pllx4 1: pllx8 opt6 = plloff pll disable. 0: pll enabled 1: pll disabled (by-passed) opt5 = pll32off 32mhz pll disable. 0: pll32 enabled 1: pll32 disabled (by-passed) opt4 = osc rc oscillator selection 0: rc oscillator on 1: rc oscillator off note: 1% rc oscillator available on st7lite15 and st7lite19 devices only opt3:2 = lvd[1:0] low voltage detection selec- tion these option bits enable the lvd block with a se- lected threshold as shown in table 22 . table 22. lvd threshold configuration opt1 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watch dog always enabled) 1: software (watchdog to be enabled by software) opt0 = wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode table 23. list of valid option combinations note 1: configuration available on st7lite15 and st7lite19 devices only note: see clock management block diagram in figure 12 configuration lvd1 lvd0 lvd off 11 highest voltage threshold ( 4.1v) 10 medium voltage threshold ( 3.5v) 01 lowest voltage threshold ( 2.8v) 00 operating conditions option bits v dd range clock source pll typ f cpu osc plloff pllx4x8 2.4v - 3.3v internal rc 1% 1) off 0.7mhz @3v 0 1 1 x4 2.8mhz @3v 0 0 0 x8 - - - - external clock or oscillator (depending on opt6:4 selec- tion) off 0-4mhz 1 1 1 x4 4mhz 1 0 0 x8 - - - - 3.3v - 5.5v internal rc 1% 1) off 1mhz @5v 0 1 1 x4 - - - - x8 8mhz @5v 0 0 1 external clock or oscillator (depending on opt6:4 selec- tion) off 0-8mhz 1 1 1 x4 - - - - x8 8 mhz 1 0 1 st7lite1 123/131 15.2 device ordering information table 24. supported part numbers part number program memory (bytes) ram (bytes) data eeprom (bytes) temp. range package st7flite10f1m6 4k flash 256 - so20 st7flite15f1m6 - -40c to 85c so20 st7flite19f1m6 128 so20 st7lite1 124/131 15.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tained from the stmicroelectronics internet site: http//www.st.com. tools from these manufacturers include c compli- ers, evaluation tools, emulators and programmers. emulators two types of emulators are available from st for the st7lite1 family: st7 dvp3 entry-level emulator offers a flexible and modular debugging and programming solution. so20 packages need a specific connection kit (refer to table 25 ) st7 emu3 high-end emulator is delivered with everything (probes, teb, adapters etc.) needed to start emulating the st7lite1. to configure it to emulate other st7 subfamily devices, the active probe for the st7emu3 can be changed and the st7emu3 probe is designed for easy interchange of tebs (target emulation board). see table 25 . in-circuit debugging kit two configurations are available from st: st7flit2-ind/usb: low-cost in-circuit debugging kit from softec microsystems. includes stx-indart/usb board (usb port) (a promotion package of 15 stflit2-ind/usb can be ordered with the following order code: stflit2-ind/15) stxf-indart/usb (a promotion package of 15 stxf-indart/usb can be ordered with the following order code: stxf-indart) flash programming tools st7-stick st7 in-circuit communication kit, a complete software/hardware package for programming st7 flash devices. it connects to a host pc parallel port and to the target board or socket board via st7 icc connector. icc socket boards provide an easy to use and flexible means of programming st7 flash devices. they can be connected to any tool that supports the st7 icc interface, such as st7 emu3, st7-dvp3, indart, st7-stick, or many third-party development tools. evaluation boards one evaluation tool is available from st: st7flit2-cos/com: streal time starter kit from cosmic software for st7flite2 and st7flite1 table 25. stmicroelectronics development tools note 1: add suffix /eu, /uk, /us for the power supply of your region. supported products emulation programming st7 dvp3 series st7 emu3 series icc socket board emulator connection kit emulator active probe & t.e.b. st7flite10 st7flite15 st7flite19 st7mdt10-dvp3 st7mdt10-20/ dvp st7mdt10-emu3 st7mdt10-teb st7sb10/123 1) st7lite1 125/131 15.4 st7 application notes table 26. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communication between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16 bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) implementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i2c peripherals an1753 software uart using 12-bit art general purpose st7lite1 126/131 an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 product optimization an 982 using st7 with ceramic renator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic discharge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscilla- tor an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop software key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 table 26. st7 application notes identification description st7lite1 127/131 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1477 emulated data eeprom with xflash memory an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programming (iap) drivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) implementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc an1796 field updates for flash based st7 applications using a pc comm port an1900 hardware implementation for st7dali-eval an1904 st7mc three-phase ac induction motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigma-delta adc with st7flite05/09 table 26. st7 application notes identification description st7lite1 128/131 16 important notes 16.1 execution of btjx instruction when testing the address $ff with the "btjt" or "btjf" instructions, the cpu may perform an in- correct operation when the relative jump is nega- tive and performs an address page change. to avoid this issue, including when using a c com- piler, it is recommended to never use address $00ff as a variable (using the linker parameter for example). 16.2 adc conversion spurious results spurious conversions occur with a rate lower than 50 per million. such conv ersions happen when the measured voltage is just between 2 consecutive digital values. workaround a software filter should be implemented to remove erratic conversion results whenever they may cause unwanted consequences. 16.3 a/ d converter accuracy for first conversion when the adc is enabled after being powered down (for example when waking up from halt, active-halt or setting the adon bit in the ad- ccsr register), the first conversion (8-bit or 10- bit) accuracy does not meet the accuracy specified in the datasheet. workaround in order to have the accuracy specified in the da- tasheet, the first conversion after a adc switch-on has to be ignored. 16.4 negative injection impact on adc accuracy injecting a negative current on an analog input pins significantly reduces the accuracy of the ad converter. whenever necessary, the negative in- jection should be prevented by the addition of a schottky diode between the concerned i/os and ground. injecting a negative current on digital input pins degrades adc accuracy especially if performed on a pin close to adc channel in use. 16.5 clearing active interrupts outside interrupt routine when an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the cc register may be corrupted. concurrent interrupt context the symptom does not occur when the interrupts are handled normally, i.e. when: - the interrupt request is cleared (flag reset or in- terrupt mask) within its own interrupt routine - the interrupt request is cleared (flag reset or in- terrupt mask) within any interrupt routine - the interrupt request is cleared (flag reset or in- terrupt mask) in any part of the code while this in- terrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following se- quence: perform sim and rim operation before and after resetting an active interrupt request ex: sim reset flag or interrupt mask rim 16.6 using pb4 as external interrupt pb4 cannot be used as an external interrupt in halt mode because the port pin pb4 is not active in this mode. st7lite1 129/131 17 revision history table 27. revision history date revision description of changes july 03 1.3 changed section 3 on page 9 and figure 3 added note on rc oscillator in section 7 on page 23 (main features) and changed section 7.1 on page 23 : removed reference to st7lite10 in rccr table changed figure 12 on page 25 (clkin/2, osc/2) added note in section 7.4 on page 26 (external clock source paragraph) changed section 13.3.1 on page 93 : f clkin instead of f osc added note in the description of osc option bit and in table 23 on page 122 dec-2004 2.0 revision number incremented from 1.3 to 2. 0 due to internal document management sys- tem change modified caution to pin n12 (so20) or pi n n7 (dip20) and added caution to pb0 and pb1 in table 1 on page 7 changed caution in section 4.4 on page 13 removed ?optional? referring to vdd in figure 4 on page 13 in section 4.5.1 on page 14 : changed 1st sentence and clarific ation of flash read-out pro- tection replaced crsr register by sicsr register in section 7.6.3 on page 32 added note in section 7.6.1 on page 29 reset delay in section 11.1.3 on page 51 changed to 30s mod00 replaced by 0ex in figure 36 on page 57 added note 2 related to exit from active halt, section 11.2.5 on page 59 changed ?output compare mode? on page 57 and note 1 in section 11.2.6 on page 60 replaced ffh by fffh in the description of ovf bit in section 11.2.6 on page 60 removed sentence relating to an effective change only after overflow for ck[1:0], page 60 replaced icap1 pin by ltic pin in section 11.3.3.3 on page 66 changed section 11.4.2 on page 70 changed section 11.4.3.3 on page 73 changed ?an interrupt is generated if spie = 1 in the spicsr register? to ?an interrupt is generated if spie = 1 in the spicr register? in description of ovr and modf bits in section 11.4.8 on page 78 added illegal opcode detection to page 1, section 7.6 on page 29 , section 12 on page 85 removed references to ?-40c to +125c? temperature range in section 13 on page 91 altered note 1 for section 13.2.3 on page 92 removing references to reset changed note 2 in section 13.2.1 on page 92 added one row in section 13.2.2 on page 92 (pb0 and pb1) changed section 13.3 on page 93 f pll value of 1mhz quoted as typical instead of a minimum in section 13.3.4.1 on page 95 in section 13.4.1 on page 99 : added note 5 and corrected f cpu in slow and slow wait modes added data for fcpu @ 1mhz into section 13.4.1 supply current table. updated figure 61. typical idd in wait vs. fcpu with correct data added v dd row in section 13.6.3 on page 102 changed section 13.7 on page 103 added caution to figure 65 on page 105 added v il min value and v ih max value in section 13.8.1 on page 105 and in section 13.9.1 on page 110 modified ?asynchronous reset pin? on page 110 ( figure 82 and figure 83 ) updated f sck in section 13.10.1 on page 112 to f cpu /4 and f cpu /2 updated adc accuracy table values on page 115 changed values in adc characteristics table on page 117 added note 4 and description relating to total pe rcentage in error and am plifier output off- set variation to the adc charac teristics subsection and table, page 117 added note 5 and description relati ng to offset variation in te mperature to adc character- istics subsection and table, page 117 st7lite1 130/131 dec-2004 2.0 changed fmp_r option bit description in section 15.1 on page 121 changed ?development tools? on page 124 added notes indicating that pb4 cannot be used as an external interrupt in halt mode, sec- tion 16.6 on page 128 and section 8.3 peripheral interrupts added ?negative injection impact on adc accuracy? on page 128 added ?clearing active interrupts outside interrupt routine? on page 128 changed table 23, ?list of valid option comb inations,? on page 122: pllx4x8 selection when pll off st7lite1 131/131 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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